View AT43USB325E-AC_2840521.PDF datasheet online --- IC-ON-LINE

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features ? avr ? 8-bit risc microcontroller with 83 ns instruction cycle time usb hub with one attached and four external ports usb keyboard function with four programmable endpoints 16 kb program memory, 512-byte data sram 32 x 8 general-purpose working registers 42 programmable i/o port pins support for 20 x 8 keyboard matrix keyboard scan inputs with pull-up resistor four led driver outputs one 8-bit timer/counter wi th separate pre-scaler one 16-bit timer/counte r with separate pre-scaler an d dual 8-, 9- or 10-bit pwm external and internal interrupt sources programmable watchdog timer 6-mhz oscillator with on-chip pll 5v operation with on-chip 3.3v power supply 64-lead lqfp package 1. description the atmel at43usb325 is an 8-bit microcontroller based on the avr risc architec- ture. by executing powerful instructions in a single clock cycle, the at43usb325 achieves throughputs approaching 12 mips. the avr core combines a rich instruc- tion set with 32 general-purpose working registers. all 32 registers are directly connected to the alu allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code effi- cient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. the at43usb325 features an on-chip 16-kbyte program memory and 512 bytes of data memory. it is supported by a standard set of peripherals such as timer/counter modules, watchdog timer and internal and external interrupt sources. the major peripheral included in the at43usb325 is the usb hub with an embedded function and gpio ports designed for use in a keyboard controller. the embedded function has 4 endpoints that makes the at43usb325 extremely suitable for key- boards supporting the consumer page as described in the ?usb usage tables?. the at43usb325 comes in two versions. the program memory of the at43usb325e is an sram that is automatically written from an external serial eeprom during power on. the at43usb325m has a masked rom program mem- ory. the two versions are pin, function and binary compatible. multimedia usb keyboard controller with embedded hub at43usb325 3355c?usb?4/05
2 3355c?usb?4/05 at43usb325 1.1 pin configuration figure 1-1. 64-lead lqfp AT43USB325E-AC figure 1-2. 64-lead lqfp at43usb325m-ac 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 pd3 pd1 pd0 dp0 dm0 dp2 dm2 dp3 dm3 vcc1 cext1 vss1 dp4 dm4 dp5 dm5 pe0 pe1 pe2 pe3 lft xtal2 xtal1 vss2 cext2 vcc2 pe4 pe5 pe6 pe7 ssn sck 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 resetn test pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pd7 pd6 pd5 pd4 miso mosi pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 pd3 pd1 pd0 dp0 dm0 dp2 dm2 dp3 dm3 vcc1 cext1 vss1 dp4 dm4 dp5 dm5 pe0 pe1 pe2 pe3 lft xtal2 xtal1 vss2 cext2 vcc2 pe4 pe5 pe6 pe7 nc pf1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 resetn test pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pd7 pd6 pd5 pd4 pf3 pf2 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7
3 3355c?usb?4/05 at43usb325 1.2 pin assignment pin# signal type pin# signal type 1 pd3 bi-directional 33 pf1/sck/oc1a bi-directional 2 pd1 bi-directional 34 nc/ssn bi-directional 3 pd0 bi-directional 35 pe7 bi-directional 4 dp0 bi-directional 36 pe6 bi-directional 5 dm0 bi-directional 37 pe5 bi-directional 6 dp2 bi-directional 38 pe4 bi-directional 7 dm2 bi-directional 39 vcc2 power supply/ground 8 dp3 bi-directional 40 cext2 output 9 dm3 bi-directional 41 vss2 power supply/ground 10 vcc1 power supply/ground 42 xtal1 input 11 cext1 output 43 xtal2 output 12 vss1 power supply/ground 44 lft output 13 dp4 bi-directional 45 pe3 bi-directional 14 dm4 bi-directional 46 pe2 bi-directional 15 dp5 bi-directional 47 pe1 bi-directional 16 dm5 bi-directional 48 pe0 bi-directional 17 resetn input 49 pb7 bi-directional 18 test input 50 pb6 bi-directional 19 pc7 bi-directional 51 pb5 bi-directional 20 pc6 bi-directional 52 pb4 bi-directional 21 pc5 bi-directional 53 pb3 bi-directional 22 pc4 bi-directional 54 pb2 bi-directional 23 pc3 bi-directional 55 pb1 bi-directional 24 pc2 bi-directional 56 pb0 bi-directional 25 pc1 bi-directional 57 pa7 bi-directional 26 pc0 bi-directional 58 pa6 bi-directional 27 pd7/intd bi-directional 59 pa5 bi-directional 28 pd6/intc bi-directional 60 pa4 bi-directional 29 pd5/intb bi-directional 61 pa3 bi-directional 30 pd4/inta bi-directional 62 pa2 bi-directional 31 pf3/so/icp bi-directional 63 pa1 bi-directional 32 pf2/si/oc1b bi-directional 64 pa0 bi-directional
4 3355c?usb?4/05 at43usb325 1.3 signal description name type function v cc1, 2 power supply/ground 5v power supply cext1, 2 output external capacitors for internal voltage regulator ? a high quality 2.2f capacitor must be connected to cext1 and 0.33 f to ce xt2 for proper operation of the chip. v ss1 , 2 power supply/ground ground xtal1 input oscillator input ? input to the inverting oscillator amplifier. xtal2 output oscillator output ? output of the inverting oscillator amplifier. lft input pll filter ? for proper operation of the pll, this pi n should be connected through a 0.01 f capacitor in parallel with a 100 ? resistor in series with a 0. 1 f capacitor to ground (vss). both capacitors must be high quality ceramic. dpo bi-directional upstream plus usb i/o ? this pin should be connected to cext1 through an external 1.5 k ? pull-up resistor. dp0 and dm0 form the differential signal pin pairs connected to the host controller or an upstream hub. dmo bi-directional upstream minus usb i/o dp[2:5] bi-directional port plus usb i/o ? each of these pins should be connected to vss th rough an external 15 k ? resistor. dp[2:5] and dm[2:5] are the differential signal pin pairs to connect downstream usb devices. dm[2:5] bi-directional port minus usb i/o ? each of these pins should be connected to vss through an external 15 k ? resistor. pa[0:7] bi-directional port a[0:7] ? bi-directional 8-bit i/o port with controlled slew rate. these pins are used as eight of the keyboard matrix column output strobes. pa[0:7] = col[0:7]. pb[0:7] bi-directional port b[0:7] ? bi-directional 8-bit i/o port controlled slew rate. these pins are used as the eight of the keyboard matrix column output strobes: pb[0:7] = col[8:15]. pb0 has a dual function: the input to timer/counter0. pc[0:7] bi-directional port c[0:7] ? bi-directional 8-bit i/o port with internal pull-ups. these pins are used as keyboard matrix row input si gnals. pc[0:7] = row [0:7]. pd[0,1,3:7] bi-directional port d[0,1,3:7] ? bi-directional i/o ports. port d[1,4:7] have dual functions as shown below: pe[0:3] bi-directional port e[0:3] ? bi-directional i/o port with controlled slew rate which can be used as four additional keyboard column output strobes, col[16:19]. pe[4:7] bi-directional pe[4:7] ? bi-directional i/o port. pe[4:7] have built-in series limiting resistors and can be used to drive leds directly port pin alternate function pb0 t0, timer/counter0 external input port pin alternate function pd1 t1, timer/counter1 external input pd3 int1, external interrupt input 1 pd4 inta, external interrupt input a pd5 intb, external interrupt input b pd6 intc, external interrupt input c pd7 intd, external interrupt input d
5 3355c?usb?4/05 at43usb325 note: signal names ending with an n are active low. pf[1:3] bi-directional port f[1:3] ? bi-directional i/o port. in the at43usb325e, these port pins have dual functions as the interface pins to the serial eeprom as shown below: nc/ssn output no connect/slave select ? in the at43usb325m this pin is not used. in the at43usb325e this pin is the spi slave select input used for enabling the serial memory during program memory downloading. test input test pin ? this pin should be tied to ground. resetn input reset ? active low 1.3 signal descrip tion (continued) name type function port pin alternate function 1 (at43usb325e only) alternate function 2 pf1 sck, spi master clock out oc1a, timer/counter1 output compare a pf2 si, spi slave data input oc1b, timer/counter1 output compare b pf3 so, spi slave data out icp , timer/counter1 input capture
6 3355c?usb?4/05 at43usb325 figure 1-3. at43usb325 enhanced risc architecture with usb keyboard controller and hub interrupt unit 8-bit timer/counter 20 strobe outputs watchdog timer 8 strobe inputs 4 led drives status and control program counter 8 x 16 program memory instruction register instruction decoder control lines 32 x 8 general-purpose registers alu 512 x 8 sram 11 gpio lines usb hub and function 16-bit timer/counter
7 3355c?usb?4/05 at43usb325 2. architectural overview the at43usb325 is a usb microcontroller with special peripherals for use as a programmable keyboard controller. the peripherals and features of the at43usb325 microcontroller are similar to those of the at90s8515, with the exception of the following modifications: a downloadable sram or masked rom for program memory no eeprom no external data memory accesses no analog comparator, spi, uart idle mode not supported additional gpio port pins: pe, pf four new external interrupt input pins: inta, intb, intc, intd usb hub with attached function the embedded usb hardware of the at43usb325 is a compound device, consisting of a 5 port hub with a permanently attached function on one port. the hub and attached function are two independent usb devices, each having its own device addresses and control endpoints. the hub has its dedicated interrupt endpoint, while the usb function has three additional program- mable endpoints with 8-byte fifos. the microcontroller always runs from a 12 mhz clock that is generated by the usb hardware. while the nominal and average period of this cl ock is 83.3 ns, it may have single cycles that deviate by 20.8 ns during a phase adjustment by the sie's clock/data separator of the usb hardware. the microcontroller shares most of the control and status registers of the megaavr ? microcon- troller family. the registers for managing the u sb operations are mapped into its sram space. the i/o section on page 17 summarizes the available i/o registers. the ?avr register set? on page 40 covers the avr registers. please refer to the atmel avr manual for more information. the fast-access register file contains 32 x 8-bi t general-purpose working registers with a single clock cycle access time. this means that during one single clock cycle, one arithmetic logic unit (alu) operation is executed. two operands are output from the register file, the operation is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-b it indirect address register pointers for data space addressing - enabling efficient address calculations. one of the three address pointers is also used as the address pointer for look-up tables in program memory. these added function registers are the 16-bit x-, y- and z-registers. the alu supports arithmetic and logic operations between registers or between a constant and a register. single register operations are also executed in the alu. figure 1-3 on page 6 shows the at43usb325 avr enhanced risc microcontroller architecture. in addition to the register operation, the co nventional memory addressing modes can be used on the register file as well. this is enabled by th e fact that the register file is assigned the 32 low- est data space addresses ($00 - $1 f), allowi ng them to be accessed as though they were ordinary memory locations.
8 3355c?usb?4/05 at43usb325 the i/o memory space contains 64 addresses for cpu peripheral functi ons as control regis- ters, timer/counters, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register file, $20 - $5f. the avr uses a harvard architecture concept ? with separate memories and buses for program and data. the program memory is executed with a single-level pipelining. while one instruction is being executed, the next instruction is pr e-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. the program memory is a download- able sram or a mask programmed rom. with the relative jump and call instructions, the whole 24k address space is directly accessed. most avr instructions have a single 16-bit word format. every program memory address con- tains a 16- or 32-bit instruction. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in th e general data sram, and consequently, the stack size is only limited by the to tal sram size and the usage of the sram. all user programs must initialize the stack pointer (sp) in the reset routine (before subroutines or interrupts are exe- cuted). the 10-bit sp is read/write accessible in the i/o space. the 512-byte data sram can be easily accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control registers in the i/o space with an additional global interrupt enable bit in the status register. all interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. the interrupts have priority in accordance with their interrupt vector position. the lower the interrupt vector address, the higher the priority.
9 3355c?usb?4/05 at43usb325 3. general-purpose register file all register operating instructions in the instruction set have direct and single cycle access to all registers. the only exception is the five consta nt arithmetic and logic instructions sbci, subi, cpi, andi, and ori between a constant and a register, and the ldi instruction for load immedi- ate constant data. these instructions apply to the second half of the registers in the register file ? r16..r31. the general sbc, sub, cp, and, and or and all other operations between two registers or on a single register apply to the entire register file. as shown in table 3-1 , each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. although not being physically imple- mented as sram locations, this memory organization provides great flexibility in access of the registers, as the x-, y-, and z-registers can be set to index any register in the file. table 3-1. avr cpu general-purpose working register register address comment r0 $00 r1 $01 r2 $02 .. r13 $0d r14 $0e r15 $0f r16 $10 r17 $11 .. r26 $1a x-register low byte r27 $1b x-register high byte r28 $1c y-register low byte r29 $1d y-register high byte r30 $1e z-register low byte r31 $1f z-register high byte
10 3355c?usb?4/05 at43usb325 3.1 x-, y- and z- registers registers r26..r31 contain some added function s to their general-purpose usage. these regis- ters are address pointers for indirect addressing of the data space. the three indirect address registers x, y, and z are defined as: in the different addressing modes these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different instructions). 3.2 arithmetic logic unit (alu) the high-performance avr alu operates in direct connection with all 32 general-purpose work- ing registers. within a single cl ock cycle, alu operations between registers in the register file are executed. the alu operations are divided into three main categories ? arithmetic, logical and bit-functions. 3.3 program memory the at43usb325e contains 16k bytes on-chip downloadable memory for program storage while the at43usb325m has a masked programmable rom. since all instructions are 16- or 32-bit words, the program memory is organized as 8k x 16. the at43usb325 program counter (pc) is 13 bits wide, thus addressing the 8,192 program memory addresses. constant tables can be allocated within the entire program memory address space (see the lpm - load program memory instruction description). the program memory of the at43usb325e is automatically written with data stored in an exter- nal serial eeprom during the chip's power on reset sequence. the power on reset is the only way the on-chip program memo ry of the at43usb325e will be written or modified. the two versions of the at43usb325 are binary compatible. a firmware written for the at43usb325e will work unaltere d on the at43usb325m. the only functional difference x-register 15 xh xl 0 7070 r27 ($1b) r26 ($1a) y-register 15 yh yl 0 7070 r29 ($1d) r28 ($1c) z-register 15 zh zl 0 7070 r30 ($1f) r31 ($1e)
11 3355c?usb?4/05 at43usb325 between the two versions is wit h respect to the serial eeprom interface pins, gpio pf[0:3]. the differences are: 3.4 spi serial eeprom in terface (at43usb325e only) the at43usb325e is designed to interface directly with a synchronous serial peripheral inter- face (spi) seeprom such as th e atmel at25hp256/512. all in structions, addr esses and data are transferred with the msb first and start with a high-to-low ssn transition. note: the spi port of the at43usb3 25e at pf[0:3] is dedicated for program memory downloading only. it cannot be accessed by the firmware program. figure 3-1. at43usb325e read sequence 3.4.1 read sequence 1. the at43usb325e asserts its ssn output pin and outputs a 3 mhz clock at sck. it continues to activate sck until the completion of the read process. 2. the at43usb325e transmits the read opcode (= 0000011) through its mosi, fol- lowed by the 16-bit byte address to be read, x0000. please note that the at43usb325e will send a 16-b yte address only. seeprom with spi that requires a 24-bit address cannot be used with the at43usb325e. 3. the seeprom then shifts out the data through its miso pin. 4. the at43usb325e de-asserts sck and ssn af ter 16k bytes data read is complete. figure 3-2. read timing port f pins at43usb325e at43usb325m pf0 slave select pin ? its output will be asserted (low) during downloading of firmware and will stay de-asserted (high) after download is completed. nc (no connect) pf1, pf2, pf3 functions as serial eeprom interface signals during downloading and as gpio pins after download is completed. gpio at43usb325e at25hp256 ssn mosi miso sck 1 2 3 4 5 6 7 8 9 10112021222324252627282930 0 2 0 1 3 4 5 6 7 0 1 2 3 13 14 15 ... data out msb high impedance instruction byte address sck mosi miso ssn
12 3355c?usb?4/05 at43usb325 3.5 sram data memory table 3-3 summarizes how the at43usb325 sram memory is organized. the lower 608 data memory locations address the register file, the i/o memory and the internal data sram. the first 96 locations address the register file + i/o memory, and the next 512 locations address the internal data sram. the five different addressing modes for the data memory cover: direct, indirect with displacement, indirect, indirect with pre-decrement and indirect with post-incre- ment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. direct addressing reaches the entire data space. the indirect with displacement mode features 63 address locations that reach from the base address given by the y- or z-register. when using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers x, y, and z are decremented and incremented. the 32 general-purpose working registers, 64 i/o registers and the 512 bytes of internal data sram in the at43usb325 are all accessible through these addressing modes. to manage the usb hardware, a special set of registers is assigned. these registers are mapped to sram space between addresses $1f00 and 1fff. table 3-3 and table 3-4 give an overview of these registers.
13 3355c?usb?4/05 at43usb325 table 3-2. sram organization register file data address space r0 $0000 r1 $0001 r30 $001e r31 $001f i/o registers $00 $0020 $01 $0021 $3e $005e $3f $005f internal sram $0060 $0061 $025e $045f usb registers $1f00 $1ffe $1fff
14 3355c?usb?4/05 at43usb325 table 3-3. usb hub and function registers address name function $1ffd frm_num_h frame number high register $1ffc frm_num_l frame number low register $1ffb glb_state global state register $1ffa sprsr suspend/resume register $1ff9 sprsie suspend/resume interrupt enable register $1ff8 sprsmsk suspend/resume interrupt mask register $1ff7 uisr usb interrupt status register $1ff6 uimskr usb interr upt mask register $1ff5 uiar usb interrupt acknowledge register $1ff3 uier usb interrupt enable register $1ff2 uovcer overcurrent detect register $1fef haddr hub address register $1fee faddr function address register $1fe7 hendp0_cntr hub endpoint 0 control register $1fe5 fendp0_cntr function endpoint 0 control register $1fe4 fendp1_cntr function endpoint 1 control register $1fe3 fendp2_cntr function endpoint 2 control register $1fe2 fendp3_cntr function endpoint 3 control register $1fdf hcsr0 hub controller endpoi nt 0 service routine register $1fdd fcsr0 function controller endpoint 0 service routine register $1fdc fcsr1 function controller endpoint 1 service routine register $1fdb fcsr2 function controller endpoint 2 service routine register $1fda fcsr3 function controller endpoint 3 service routine register $1fd7 hdr0 hub endpoint 0 fifo data register $1fd5 fdr0 function endpoint 0 fifo data register $1fd4 fdr1 function endpoint 1 fifo data register $1fd3 fdr2 function endpoint 2 fifo data register $1fd2 fdr3 function endpoint 3 fifo data register $1fcf hbyte_cnt0 hub endpoint 0 byte count register $1fcd fbyte_cnt0 function endpoint 0 byte count register $1fcc fbyte_cnt1 function endpoint 1 byte count register $1fcb fbyte_cnt2 function endpoint 2 byte count register $1fca fbyte_cnt3 function endpoint 3 byte count register $1fc7 hstr hub status register $1fc5 hpcon hub port control register $1fbc hpstat5 hub port 5 status register
15 3355c?usb?4/05 at43usb325 $1fbb hpstat4 hub port 4 status register $1fba hpstat3 hub port 3 status register $1fb9 hpstat2 hub port 2 status register $1fb8 hpstat1 hub port 1 status register $1fb4 hpscr5 hub port 5 status change register $1fb3 hpscr4 hub port 4 status change register $1fb2 hpscr3 hub port 3 status change register $1fb1 hpscr2 hub port 2 status change register $1fb0 hpscr1 hub port 1 status change register $1fac pstate5 hub port 5 bus state register $1fab pstate4 hub port 4 bus state register $1faa pstate3 hub port 3 bus state register $1fa9 pstate2 hub port 2 bus state register $1fa7 hcar0 hub endpoint 0 control and acknowledge register $1fa5 fcar0 function endpoint 0 control and acknowledge register $1fa4 fcar1 function endpoint 1 control and acknowledge register $1fa3 fcar2 function endpoint 2 control and acknowledge register $1fa2 fcar3 function endpoint 3 control and acknowledge register table 3-3. usb hub and function registers (continued) address name function
16 3355c?usb?4/05 at43usb325 table 3-4. usb hub and function registers name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 glb_state $1ffb ? kb int en ? susp flg resume flg rmwupe confg hadd en sprsr $1ffa intd intc intb inta - frwup rsm glb susp sprsie $1ff9 intd en intc en intb en inta en - frwup ie rsm ie glb susp ie sprsmsk $1ff8 intd msk intc msk intb msk inta msk - frwup msk rsm msk glb susp msk uisr $1ff7 sof int eof2 int - fep3 int h ep0 int fep2 int fep1 int fep0 int uimskr $1ff6 sof msk sof2 msk - fep3 msk hep0 msk fep2 msk fep1 msk fep0 msk uiar $1ff5 sof intack eof2 intack - fep3 intack hep0 intack fep2 intack fep1 intack fep0 intack uier $1ff3 sof ie eof2 ie - fep3 ie hep0 ie fep2 ie fep1 ie fep0 ie uovcer $1ff2 ? ? ? ? ? ovc ? ? iscr $1ff1 isc71 isc70 isc61 isc60 isc51 isc50 isc41 isc40 haddr $1fef saen hadd6 hadd5 h add4 hadd3 hadd2 hadd1 hadd0 faddr $1fee fen fadd6 fadd5 fadd4 fadd3 fadd2 fadd1 fadd0 hendp0_cntr $1fe7 epen ? ? ? dtgle epdir eptype1 eptype0 fendp0_cntr $1fe5 epen ? ? ? dtgle epdir eptype1 eptype0 fendp1_cntr $1fe4 epen ? ? ? dtgle epdir eptype1 eptype0 fendp2_cntr $1fe3 epen ? ? ? dtgle epdir eptype1 eptype0 fendp3_cntr $1fe2 epen - - - dtgle epdir eptype1 eptype0 hcsr0 $1fdf ? ? ? ? stall sent rx se tup rx out packet tx cemplete fcsr0 $1fdd ? ? ? ? stall sent rx setup rx out packet tx complete fcsr1 $1fdc ? ? ? ? stall sent rx setup rx out packet tx complete fcsr2 $1fdb ? ? ? ? stall sent rx setup rx out packet tx complete fcsr3 $1fda - - - - stall sent - rx out packet tx cmplete hdr0 $1fd7 data7 data6 data5 data4 data3 data2 data1 data0 f d r 0 $ 1 f d 5 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 f d r 1 $ 1 f d 4 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 f d r 2 $ 1 f d 3 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 f d r 3 $ 1 f d 2 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 hbyte_cnt0 $1fcf ? ? bytct5 bytct4 bytct3 bytct2 bytct1 bytct0 fbyte_cnt0 $1fcd ? ? bytct5 bytct4 bytct3 bytct2 bytct1 bytct0 fbyte_cnt1 $1fcc ? ? bytct5 bytct4 bytct3 bytct2 bytct1 bytct0 fbyte_cnt2 $1fcb ? ? bytct5 bytct4 bytct3 bytct2 bytct1 bytct0 fbyte_cnt3 $1fca - - - bytct4 bytct3 bytct2 bytct1 bytct0 hstr $1fc7 ? ? ? ? ovlsc lpsc ovi lps hpcon $1fc5 ? hpcon2 hpcon1 hpcon0 ? hpadd2 hpadd1 hpadd0 hpstat5 $1fbc - lsp ppstat prstat poci psstat pestat pcstat hpstat4 $1fbb - lsp ppstat prstat poci psstat pestat pcstat hpstat3 $1fba ? lsp ppstat prstat poci psstat pestat pcstat hpstat2 $1fb9 ? lsp ppstat prstat poci psstat pestat pcstat hpstat1 $1fb8 ? lsp ppstat prstat poci psstat pestat pcstat hpscr5 $1fb4 - - - rstsc pocic pssc pesc pcsc hpscr4 $1fb3 - - - rstsc pocic pssc pesc pcsc hpscr3 $1fb2 ? ? ? rstsc pocic pssc pesc pcsc hpscr2 $1fb1 ? ? ? rstsc pocic pssc pesc pcsc hpscr1 $1fb0 ? ? ? rstsc pocic pssc pesc pcsc pstat5 $1fac ? ? ? ? ? ? dpstate dmstate pstat4 $1fab ? ? ? ? ? ? dpstate dmstate pstat3 $1faa ? ? ? ? ? ? dpstate dmstate pstat2 $1fa9 ? ? ? ? ? ? dpstate dmstate hcar0 $1fa7 ctl dir data end force stall tx packet ready sta ll_sent-ack rx_setup_ack rx_ou t_packet_ack tx_complete-ack fcar0 $1fa5 ctl dir data end force stall t x packet ready stall_sent-ack rx_setup_ ack rx_out_packet_ack tx_complete-ack
17 3355c?usb?4/05 at43usb325 3.6 i/o memory the i/o space definition of the at43usb325 is shown in the following table: fcar1 $1fa4 ctl dir data end force stall t x packet ready stall_sent-ack rx_setup_ ack rx_out_packet_ack tx_complete-ack fcar2 $1fa3 ctl dir data end force stall t x packet ready stall_sent-ack rx_setup_ ack rx_out_packet_ack tx_complete-ack fcar3 $1fa2 ctl dir data end force stall tx pack rd y stall_sent_ack - rx_out_packet_ack tx_complete_ack table 3-4. usb hub and function registers (continued) name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 table 3-5. i/o memory space i/o (sram) address name function $3f ($5f) sreg status register $3e ($5e) sph stack pointer high $3d ($5d) spl stack pointer low $3b ($5b) gimsk general interrupt mask register $3a ($5a) gifr general interrupt flag register $39 ($59) timsk timer/counter interrupt mask register $38 ($58) tifr timer/counte r interrupt mask register $35 ($55) mcucr mcu general control register $33 ($53) tccr0 timer/counter0 control register $32 ($52) tcnt0 timer/counter0 (8 bit) $2f ($4f) tccr1a timer/count er1 control register a $2e ($4e) ttcr1b timer/counter1 control register b $2d ($52) tcnt1h timer/counter1 high byte $2c ($52) tcnt1l timer/counter1 low byte $2b ($4b) ocr1ah timer/counter1 output compare register a high byte $2a ($4a) ocr1al timer/counter1 output compare register a low byte $29 ($49) ocr1bh timer/counter1 output compare register b high byte $28 ($48) ocr1bl timer/counter1 output compare register b low byte $25 ($45) icr1h t/c 1 input capture register high byte $24 ($44) icr1l t/c 1 input capture register low byte $21 ($41) wdtcr watchdog timer counter register $1b ($4b) porta data register, port a $1a ($3a) ddra data direction register, port a $19 ($39) pina input pins, port a $18 ($38) portb data register, port b $17 ($37) ddrb data direction register, port b $16 ($36) pinb input pins, port b
18 3355c?usb?4/05 at43usb325 all at43usb325 i/o and peripherals, except for the usb hardware registers, are placed in the i/o space. the i/o locations are accessed by the in and out instructions transferring data between the 32 general-purpose working registers and the i/o space. i/o registers within the address range $00 ? $1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. refer to the instruction set documentations of the avr for more details. when using the i/o specific commands, in and out, the i/o address $00 ? $3f must be used. when addressing i/o regis- ters as sram, $20 must be added to this address. all i/o register addresses throughout this document are shown with the sram address in parentheses. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addresses should never be written. 3.7 usb hub a block diagram of the usb hardware of the at43usb325 is shown in figure 3-3 . the usb hub of the at43usb325 has 5 downstream ports. the embedded function is permanently attached to port 1. ports 2, 3, 4 and 5 are available as external ports. the actual number of ports used is strictly defined by the firmware of the at43usb325 and can vary from 0 to 4. because the exact configuration is defined by firmware, these ports may even function as permanently attached ports as long as the hub descriptor identifies them as such. 3.7.1 usb function the embedded usb function has its own device address and has a default endpoint plus 3 other programmable endpoints with their own 8-byte fifos. endpoints 1 and 2 can be programmed as interrupt in or out or bulk in or out endpoints. $15 ($35) portc data register, port c $14 ($34) ddrc data direction register, port c $13 ($33) pinc input pins, port c $12 ($32) portd data register, port d $11 ($31) ddrd data direction register, port d $10 ($30) pind input pins, port d $06 ($26) portf data register, port f $05 ($25) ddrf data direction register, port f $04 ($24) pinf input pins, port f $03 ($23) porte data register, port e $02 ($22) ddre data direction register, port e $01 ($21) pine input pins, port e table 3-5. i/o memory space (continued) i/o (sram) address name function
19 3355c?usb?4/05 at43usb325 figure 3-3. usb hardware hub repeater serial interface engine avr microcontroller data address control hub interface unit port 1 function interface unit port 0 xcvr port 2 xcvr port 5 xcvr port 4 xcvr port 3 xcvr
20 3355c?usb?4/05 at43usb325 4. functional description 4.1 on-chip power supply the at43usb325 contains two on-chip power supplies that generate 3.3v with a capacity of 30 ma each from the 5v power input. the on-chip power supplies are intended to supply the at43usb325 internal circuit and the 1.5k pull-up resistor only and should not be used for other purposes. external 2.2 f filter capacitors are required at the power supply outputs, cext1 and cext2. the internal power supplies can be disabled as described in the next paragraph. the user should be careful when the gpio pins ar e required to supply high-load currents. if the application requires that the gpio supply curr ents beyond the capability of the on-chip power supply, the at43usb325 should be supplied by an external 3.3v power supply. in this case, the 5v v cc power supply pin should be left unconnected and the 3.3v power supplied to the chip through the cext1 and cext2 pins. 4.2 i/o pin c haracteristics the i/o pins of the at43usb325 should not be directly connected to voltages less than v ss or more than the voltage at the cext pins. if it is necessary to violate this rule, insert a series resis- tor between the i/o pin and the source of the external signal source that limits the current into the i/o pin to less than 2 ma. under no circ umstance should the external voltage exceed 5.5v. to do so will put the chip under excessive stress. 4.3 oscillator and pll all clock signals required to op erate the at43usb325 are derived from an on -chip oscillator. to reduce emi and power dissipation , the oscillator is designed to operate with a 6 mhz crystal. an on-chip pll generates the high frequency for the clock/data separator of the serial interface engine. in the suspended state, the oscillator ci rcuitry is turned off. the oscillator of the at43usb325 is a special, low-drive type, designed to work with most crys- tals without any external components. the crystal must be of the parallel resonance type requiring a load capacitance of about 10 pf. if the crystal requires a higher value capacitance, external capacitors can be added to the two terminals of the crystal and ground to meet the required value. to assure quick start-up, a crystal with a high q, or low esr, should be used. to meet the usb hub frequency accuracy and stability requirements for hubs, the crystal should have an accuracy and stability of better than 100 ppm. the use of a ceramic resonator in place of the crystal is not recommended because a resonator would not have the necessary frequency accuracy and stability. the clock can also be externally sourced. in this case, connect the clock source to the xtal1 pin, while leaving xtal2 pin floating. the swit ching level at the osc1 pin can be as low as 0.47v and a cmos device is required to drive this pin to maintain good noise margins at the low switching level. for proper operation of the pll, an external rc filter consisting of a series rc network of 100 ? and 0.1 f in parallel with a 0.01 f capacitor must be connected from the lft pin to v ss . use only high-quality ceramic capacitors.
21 3355c?usb?4/05 at43usb325 figure 4-1. oscillator and pll 4.4 reset and inte rrupt handling the at43usb325 provides 12 different interrupt sources with 4 separate reset vectors, each with a separate program vector in the program memory space. nine of the interrupt sources share 2 interrupt reset vectors. these nine are the usb related interrupts. all interrupts are assigned individual enable bits which must be set (one) together with the i-bit in the status regis- ter in order to enable the interrupt. the lowest addresses in the program memory space are automatically defined as the reset and interrupt vectors. the complete list of vectors is shown in table 4-1 . the list also determines the priority levels of the different interrupts. the lower the address, the higher is the priority level. reset has the highest priority, and next is int0 ? the usb suspend and resume interrupt, etc. at43usb325 xtal1 xtal2 lft y1 6.000 mhz u1 c2 0.01 uf c1 0.22 uf r1 100 table 4-1. reset and interrupt vectors vector no. program address source interrupt definition 1 $000 reset external reset, power-on reset and watchdog reset 2 $002 int0 usb suspend and resume 3 $004 int1 external interrupt request 1 4 $006 timer1 capt timer/counter1 capture event 5 $008 timer1 compa timer/counter1 compare match a 6 $00a timer1 compb timer/counter1 compare match b 7 $00c timer1, ovf timer/counter1 overflow 8 $00e timer0, ovf timer/counter0 overflow 13 $018 usb hw usb hardware
22 3355c?usb?4/05 at43usb325 the most typical and general program setup for the reset and interrupt vector addresses are: usb related interrupt events are routed to reset vectors 13 and 2 through a separate set of inter- rupt, interrupt enable and interrupt mask registers that are mapped to the data sram space. these interrupts must be enabled though their control register bits. in the event an interrupt is generated, the source of the interrupt is identi fied by reading the interrupt registers. the usb frame and transaction related interrupt events, such as start of frame interrupt, are grouped in one set of registers: usb interrupt flag register, usb interrupt enable register and usb inter- rupt mask register. the usb bus reset and suspend/resume are grouped in another set of registers: suspend/resume register, suspend /resume interrupt enable register and sus- pend/resume interrupt mask register. some applications may include firmware routines lasting for long periods that can not be inter- rupted. at the same time, other less critical events may need attention after the critical routine is completed. the at43usb325 solves this problem by having interrupt mask registers in addition to the interrupt enable registers of the usb related interrupts. the difference between the mask and enable registers is: the enable register enables the interrupt so it is captured into the interrupt register. if it is not enabled, and an interrupt oc curs, the interrupt will be lost. the mask register merely masks the interrupt from interrupting the cpu. upon unmasking, the pending interrupt is triggered. address labels code comments $000 jmp reset ; reset handler $002 jmp ext_int0 ; irq0 handler $00e jmp tim0_ovf ; timer0 overflow handler $018 jmp usb_hw ; usb handler ; $00d main: ldi r16, high (ramend) ; main program start $00e out sph, r16 $00f ldi r16, low (ramend) $010 out spl, r16 $011 xxx ... ... ... ...
23 3355c?usb?4/05 at43usb325 figure 4-2. at43usb325 interrupt structure 4.5 reset sources the at43usb325 has four sources of reset: power-on reset ? the mcu is reset when the supply voltage is below the power-on reset threshold. external reset ? the mcu is reset when a low level is present on the reset pin for more than 50 ns. watchdog reset ? the mcu is reset when the watchdog timer period expires and the watchdog is enabled. usb reset ? the at43usb325 has a feature to separate the usb and microcontroller resets. this feature is enabled by setting the bus int en, bit 3 of the sprsie register. a usb bus reset is defined as a se0 (single ended zero) of at least 4 slow speed usb clock cycles received by port0. the internal reset pulse to the usb hardware and microcontroller lasts for 24 o scillator periods. ? resets not separated: a usb bus reset will also reset the microcontroller. suspend/resume register suspend/resume interrupt enable register suspend/resume interrupt mask register usb interrupt flag register usb interrupt enable register usb interrupt mask register usb int0 reset microcontroller interrupt logic 13 timer0 ovf 8 2 1 sof eof2 fep2 fep1 fep0 hep0 frmwup rsm glb susp fep3 timer ovf 7 compa 5 compb 6 int1 3 bus reset inta intb intc intd
24 3355c?usb?4/05 at43usb325 ? separated reset: a usb bus reset will on ly reset the usb hardware, while an interrupt to the microcontrolle r will be generated if the bus int msk bit, bit 3 of sprsmsk register, is also set. when the usb hardware is reset, the compound device is de-configured and has to be re-enu- merated by the host. when the microcontroller is reset, all i/o registers are then set to their initial values, and the program starts execution from address $000. the instruction placed in address $000 must be a jmp instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. the circuit diagram in figure 4-3 shows the reset logic. figure 4-3. reset logic 4.6 power-on reset a power-on reset (por) circuit ensures that the device is reset from power-on. an internal timer clocked from the wa tchdog timer oscillator pr events the mcu from starting until after a cer- tain period after v cc has reached the power-on threshold voltage, regardless of the v cc rise time. if the build-in start-up delay is sufficient, reset can be connected to v cc directly or via an external pull-up resistor. by holdi ng the pin low for a period after v cc has been applied, the power-on reset period can be extended. fstrt cntr reset usb reset or por ckt reset ckt watchdog timer divider 14-bit cntr vcc rstn 1-mhz clock s r on
25 3355c?usb?4/05 at43usb325 4.7 external reset an external reset is generated by a low-level on the reset pin. reset pulses longer than 200 ns will generate a reset. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage - v rst on its positive edge, the delay timer starts the mcu after the time-out period t tout has expired. figure 4-4. external reset during operation 4.8 watchdog timer reset when the watchdog times out, it will generate a short reset pulse of 1 xtal cycle duration. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . figure 4-5. watchdog reset during operation t tout v rst vcc reset time-out internal reset t tout vcc reset wdt time-out reset time-out 1 xtal cycle internal reset
26 3355c?usb?4/05 at43usb325 4.9 non-usb related interrupt handling the at43usb325 has two non-usb 8-bit interr upt mask control registers; gimsk (general interrupt mask register) and timsk (timer/counter interrupt mask register). when an interrupt occurs, the global interrupt enable i-bit is cleared (zero) and all interrupts are disabled. the user software can set (one) the i-bit to enable nested interrupts. the i-bit is set (one) when a return from interrupt instruction, reti, is executed. for interrupts triggered by events that can remain static (e.g. the output compare register1 matching the value of timer/counter1) the interrupt flag is set when the event occurs. if the interrupt flag is cleared and the in terrupt condition persis ts, the flag will not be set until the event occurs the next time. when the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hard-ware clears the corresponding flag that generated the interrupt. some of the interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. if one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set (one), and will be exec uted by order of priority. note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is active. 4.9.1 general interrupt mask register ? gimsk bit 7 ? int1: external interrupt request 1 enable when the int1 bit is set (one) and the i-bit in the status register (sreg) is set (one), the exter- nal pin interrupt is enabled. the interrupt sense control1 bits 1/0 (isc11 and isc10) in the mcu general control register (mcucr) defines whether the external interrupt is activated on rising or falling edge of the int1 pin or level sensed. activity on th e pin will cause an interrupt request even if int1 is configured as an output. the corresponding interrupt of external interrupt request 1 is executed from program memory address $004. see also ?external interrupts? on page 29 . bit 6 ? int0: interrupt request 0 (suspend/resume interrupt) enable when the int0 bit is set (one) and the i-bit in the status register (sreg) is set (one), the exter- nal pin interrupt is enabled. the interrupt sense control0 bits 1/0 (isc01 and isc00) in the mcu general control register (mcucr) defines whether the external interrupt is activated on rising or falling edge of the int0 pin or level sensed. activity on th e pin will cause an interrupt request even if int0 is configured as an output. the corresponding interrupt of interrupt request 0 is executed from program memory address $002. see also ?external interrupts? on page 29 . bit 7 6 5 4 3 210 $3b ($5b) int1 int0 ? ? ? ? ? ? gimsk read/write r/w r/w r r r r r r initial value 0 0 0 0 0 0 0 0
27 3355c?usb?4/05 at43usb325 bits 5..0 ? res: reserved bits these bits are reserved bits in the at43usb325 and always read as zero. 4.9.2 general interrupt flag register ? gifr bit 7 ? intf1: external interrupt flag1 when an event on the int1 pin triggers an interrupt request, intf1 becomes set (one). if the i- bit in sreg and the int1 bit in gimsk are set ( one), the mcu will jump to the interrupt vector at address $004. the flag is cleared when the interrup t routine is executed. alternatively, the flag can be cleared by writing a logical one to it. bit 6 ? intf0: interrupt flag0 (suspend/resume interrupt flag) when an event on the int0 (that is, a usb event-related interrupt) triggers an interrupt request, intf0 becomes set (one). if the i-bit in sreg and the int0 bit in gimsk are set (one), the mcu will jump to the interr upt vector at address $002. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. bits 5..0 ? res: reserved bits these bits are reserved bits in the at43usb325 and always read as zero. 4.9.3 timer/counter interrupt mask register ? timsk bit 7 ? toie1: timer/counter1 overflow interrupt enable when the toie1 bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 overflow interrupt is enabled. the corresponding interrupt (at vector $006) is executed if an overflow in timer/counter1 occurs, i.e., when the tov1 bit is set in the timer/counter interrupt flag register (tifr). bit 6 ? oce1a: timer/counter1 output comparea match interrupt enable when the ocie1a bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 comparea match interrupt is enabled. the corresponding interrupt (at vector $004) is executed if a comparea match in timer/counter1 occurs, i.e., when the ocf1a bit is set in the tifr. bit 5 ? ocie1b: timer/counter1 output compareb match interrupt enable when the ocie1b bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 compareb match interrupt is enabled. the corresponding interrupt (at vector bit 7 6 543210 $3a ($5a) intf1 int f0 ? ? ? ? ? ? gifr read/write r/w r/w r r r r r r initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 210 $39 ($59) toie1 ocie1a ocie1nb ? ticie1 ? toie0 ? timsk read/write r/w r/w r/w r r/w r r/w r initial value 0 0 0 0 0 0 0 0
28 3355c?usb?4/05 at43usb325 $005) is executed if a compareb match in timer/counter1 occurs, i.e., when the ocf1b bit is set in the tifr. bit 4 ? res: reserved bit this bit is a reserved bit in the at43usb325 and always reads zero. bit 3 ? ticie1: timer/counter1 input capture interrupt enable when the ticie1 bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 input capture event interrupt is enabled. the corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, icp, i.e., when the icf1 bit is set in the tifr. bit 2 ? res: reserved bit this bit is a reserved bit in the at43usb325 and always reads zero. bit 1 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is set (one) and the i-bit in the status register is set (one), the timer/counter0 overflow interrupt is enabled. the corresponding interrupt (at vector $007) is executed if an overflow in timer/counter0 occurs, i.e., when the tov0 bit is set in the tifr. bit 0 ? res: reserved bit this bit is a reserved bit in the at43usb325 and always reads zero. 4.9.4 timer/counter interrupt flag register ? tifr bit 7 ? tov1: timer/counter1 overflow flag the tov1 is set (one) when an overflow occurs in timer/counter1. tov1 is cleared by the hard- ware when executing the corresponding interrupt handling vector. alternatively, tov1 is cleared by writing a logic one to the flag. when the i-bit in sreg, and toie1 (timer/counter1 overflow interrupt enable), and tov1 are set (one), the timer/counter1 overflow interrupt is executed. in pwm mode, this bit is set when timer/counter1 changes counting direction at $0000. bit 6 ? ocf1a: output compare flag 1a the ocf1a bit is set (one) when compare match occurs between the timer/counter1 and the data in ocr1a - output compare register 1a. ocf1a is cleared by the hardware when execut- ing the corresponding interrupt handling vector. alternatively, ocf1a is cleared by writing a logic one to the flag. when the i-bit in sre g, and ocie1a (timer/counter1 compare match interrupta enable), and the ocf1a are set (one), the timer/counter1 compare a match inter- rupt is executed. bit 5 ? ocf1b: output compare flag 1b the ocf1b bit is set (one) when compare match occurs between the timer/counter1 and the data in ocr1b - output compare register 1b. ocf1b is cleared by the hardware when execut- bit 7 6 5 4 3 210 $38 ($58) tov1 ocf1a ocifb ? icf1 ? tov0 ? tifr read/write r/w r/w r/w r r/w r r/w r initial value 0 0 0 0 0 0 0 0
29 3355c?usb?4/05 at43usb325 ing the corresponding interrupt handling vector. alternatively, ocf1b is cleared by writing a logic one to the flag. when the i-bit in sre g, and ocie1b (timer/counter1 compare match interruptb enable), and the ocf1b are set (one), the timer/counter1 compare b match inter- rupt is executed. bit 4 ? res: reserved bit this bit is a reserved bit in the at43usb325 and always reads zero. bit 3 ? icf1: - input capture flag 1 the icf1 bit is set (one) to flag an input capture event, indicating that the timer/counter1 value has been transferred to the input capture register - icr1. icf1 is cleared by the hardware when executing the corresponding interrupt handling vector . alternatively, icf1 is cleared by writing a logic one to the flag. when the sreg i-bit, and ticie1 (timer/counter1 input capture interrupt enable), and icf1 are set (one), the timer/counter1 capture interrupt is executed. bit 2 ? res: reserved bit this bit is a reserved bit in the at43usb325 and always reads zero. bit 1 ? tov: timer/counter0 overflow flag the bit tov0 is set (one) when an overflow occurs in timer/counter0. tov0 is cleared by the hardware when executing the corresponding interrupt handling vector. alternatively, tov0 is cleared by writing a logic one to the flag. w hen the sreg i- bit, and toie0 (timer/counter0 overflow interrupt enable), and tov0 are set (one), the timer/counter0 overflow interrupt is executed. bit 0 ? res: reserved bit this bit is a reserved bit in the at43usb325 and always reads zero. 4.10 external interrupts the external interrupts are triggered by the int1 and inta/b/c/d pins. observe that, if enabled, the int1 interrupt will trigger ev en if the int1 pin is configur ed as an output. this feature pro- vides a way of generating a software interrupt. a falling or rising edge or a low level can trigger the external interrupts. this is set up as indica ted in the specification for the mcu control regis- ter ? mcucr and the interrupt sense control register ? iscr. when int1 is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. int1 is set up as described in the specificatio n for the mcu control register ? mcucr. 4.11 interrupt response time the interrupt execution response for all the enabled avr interrupts is 4 clock cycles minimum. 4 clock cycles after the interrupt flag has been set, the program vector address for the actual inter- rupt handling routine is executed. during th is 4 clock cycle period, the program counter (2 bytes) is pushed onto the stack, and the stack poin ter is decremented by 2. the vector is nor- mally a jump to the interrupt routine, and this jump takes 3 clock cycles. if an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. a return from an interrupt handling routine (same as for a subroutine call routine) takes 4 clock cycles. during these 4 clock cycles, the program counter (2 bytes) is popped back from the stack, the stack pointer is incremented by 2, and the i flag in sreg is set. when the avr exits
30 3355c?usb?4/05 at43usb325 from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. 4.11.1 mcu control register ? mcucr bit 7, 6 ? res: reserved bits bit 5 ? se: sleep enable the se bit must be set (1) to make the mcu en ter the sleep mode when the sleep instruction is executed. to avoid the mcu entering the slee p mode, unless it is the programmer's purpose, it is recommended to set the sleep enable se bit just before the execution of the sleep instruction. bit 4 ? sm: sleep mode this bit selects between the two available sleep modes. when sm is cleared (zero), idle mode is selected as sleep mode. when sm is set (1), power down mode is selected as sleep mode. the at43usb325 does not support the idle mode and sm should always be set to one when enter- ing the sleep mode. bit 3, 2 ? isc11, isc10: interrupt sense control 1 bit 1 and bit 0 the external interrupt 1 is activated by the exte rnal pin int1 if the sreg i-flag and the corre- sponding interrupt mask in the gimsk is set. the level and edges on the external int1 pin that activate the interrupt are defined in the following table: bit 7 6 5 4 3 2 1 0 $35 ($55) ? ? se sm isc11 isc10 ? ? mcucr read/write r r r/w r/w r/w r/w r r initial value 0 0 0 0 0 0 0 0 table 4-2. int1 sense control isc11 isc10 description 0 0 the low level of int1 generates an interrupt request. 01reserved. 1 0 the falling edge of int1 generates an interrupt request. 1 1 the rising edge of int1 generates an interrupt request.
31 3355c?usb?4/05 at43usb325 4.12 usb interrupt sources the usb interrupts are described below. all interrupts have individual enabl e, status, and mask bits through the interrupt enable register and interrupt mask register. the suspend and resume interrupts are cleared by writing a 0 to the particular interrupt bit. all other interrupts are cleared when the microcontroller sets a bit in an interrupt acknowledge register. table 4-3. usb interrupt sources interrupt description sof received whenever usb hardware decodes a valid start of frame. the frame number is stored in th e two frame number registers. eof2 activated whenever the hub's frame timer reaches its eof2 time point. function ep0 interrupt see ?control transfers at control end-point ep0? on page 64 for details. function ep1 interrupt for an out endpoint it indicates that function endpoint 1 has received a valid out packet and that the data is in the fifo. for an in endpoint it means that the endpoint has received an in token, sent out the data in the fifo and received an ack from the host. the fifo is now ready to be written by new data from the microcontroller. function ep2 interrupt for an out endpoint it indicates that function endpoint 2 has received a valid out packet and that the data is in the fifo. for an in endpoint it means that the endpoint has received an in token, sent out the data in the fifo and received an ack from the host. the fifo is now ready to be written by new data from the microcontroller. function ep3 interrupt for an out end-point it indicates that function end-point 3 has received a valid out packet and that the data is in the fifo. for an in end-point it means that the end-point has received an in token, sent out the data in the fifo and received an ack from the host. the fifo is now ready to be written by new data from the microcontroller. hub ep0 interrupt see ?control transfers at control end-point ep0? on page 64 for details. frwup usb hardware has received a embedded function remote wakeup request. glb susp usb hardware has received global suspend signaling and is preparing to put the hub in the suspend mode. the microcontroller's firmware should place the embedded function in the suspend state. rsm usb hardware received resume signaling and is propagating the resume signaling. the microcontroller's firmware should take the embedded function out of the suspended state. bus reset usb hardware received a usb bus reset. this applies only in cases where a separation between usb bus reset and microcontroller reset is required. be very careful when using this feature.
32 3355c?usb?4/05 at43usb325 4.13 usb endpoint interrupt sources an assertion or activation of one or more bits in the endpoint's control and status register trig- gers the endpoint interrupts. these triggers are different for control and non-control endpoints as described in the table below. please refer to the control and status register for more information. 4.13.1 usb interrupt status register ? uisr bit 7 ? sof int: start of frame interrupt this bit is asserted after the usb hardware receives a valid sof packet. bit 6 ? eof2 int: eof2 interrupt this bit is asserted 10 clocks before the expected start of a frame. bit 5 ? res: reserved bit this bit is reserved an d always reads as zero. bit 4 ? fep3 int: function end-point 3 interrupt bit 3 ? hep0 int: hub endpoint 0 interrupt bit 2 ? fep2 int: function endpoint 2 interrupt bit 1 ? fep1 int: function endpoint 1 interrupt bit 0 ? fep0 int: function endpoint 0 interrupt the hub and function interrupt bits will be set by the hardware whenever t he following bits in the corresponding endpoint's control and status register are modified by the usb hardware: 1. rx out packet is set (control and out endpoints) 2. tx packet ready is cleared and tx complete is set (control and in endpoints) 3. rx setup is set (control endpoints only) 4. tx complete is set table 4-4. usb endpoint interrupt sources bit endpoint type rx_out_packet control, out tx_complete control, in stall_sent control, in rx_setup control bit 7 6 5 4 3 2 1 0 $1ff7 sof int eof2 int ? fe3 int hep0 int fe2 int fe1 int fe0 int uisr read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0
33 3355c?usb?4/05 at43usb325 4.13.2 usb interrupt mask register ? uimskr bit 7 ? sof imsk: enable start of frame interrupt mask when the sof imsk bit is set (1), the start of frame interrupt is masked. bit 6 ? eof2 imsk: enable eof2 interrupt when the eof2 imsk bit is set (1), the eof2 interrupt is masked. bit 5 ? res: reserved bit this bit is reserved and always read as zero. bit 4 ? fep3 imsk: function end-point 3 interrupt mask when the fe3 imsk bit is set (1), the function end-point 3 interrupt is masked. bit 3 ? hep0 imsk: enab le endpoint 0 interrupt when the hep0 imsk bit is set (1), the hub endpoint 0 interrupt is masked. bit 2 ? fep2 imsk: enable endpoint 2 interrupt when the fe2 imsk bit is set (1), the function endpoint 2 interrupt is masked. bit 1 ? fep1 imsk: enable endpoint 1 interrupt when the fe1 imsk bit is set (1), the function endpoint 1 interrupt is masked. bit 0 ? fep0 imsk: enable endpoint 0 interrupt when the fe0 imsk bit is set (1), the function endpoint 0 interrupt is masked. bit 7 6 5 4 3 2 1 0 $1ff6 sof imsk eof2 imsk ? fep3 imsk hep0 imsk fep2 imsk fep1 imsk fep0 imsk uimskr read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
34 3355c?usb?4/05 at43usb325 4.13.3 usb interrupt acknowledge register ? uiar bit 7 ? sof intack: start of frame interrupt acknowledge the microcontroller firmware writes a 1 to this bit to clear the sof int bit. bit 6 ? eof2 intack: eof2 interrupt acknowledge the microcontroller firmware writes a 1 to this bit to clear the eof2 int bit. bit 5 ? res: reserved bit this bit is reserved and is always read as zero. bit 4 ? fep3 intack: function end-point 3 interrupt acknowledge the microcontroller firmware writes a 1 to this bit to clear the fep3 int bit. bit 3 ? hep0 intack: hub endpoint 0 interrupt acknowledge the microcontroller firmware writes a 1 to this bit to clear the hep0 int bit. bit 2 ? fep2 intack: function endpoint 2 interrupt acknowledge the microcontroller firmware writes a 1 to this bit to clear the fep2 bit. bit 1 ? fep1 intack: function endpoint 1 interrupt acknowledge the microcontroller firmware writes a 1 to this bit to clear the fep1 bit. bit 0 ? fep0 intack: function endpoint 0 interrupt acknowledge the microcontroller firmware writes a 1 to this bit to clear the fep0 int bit. bit 7 6 5 4 3 2 1 0 $1ff5 sof intack eof2 intack ? fep3 intack hep0 intack fep2 imsk fep1 intack fep0 intack uiar read/writew wrw www w initial value 0 0 0 0 0 0 0 0
35 3355c?usb?4/05 at43usb325 4.13.4 usb interrupt enable register ? uier bit 7 ? sof ie: enable start of frame interrupt when the sof ie bit is set (1), the start of frame interrupt is enabled. bit 6 ? eof2 ie: enable eof2 interrupt when the eof2 ie bit is set (1), the eof2 interrupt is enabled. bit 5 ? res: reserved bit this bit is reserved and always read as zero. bit 4 ? fep3 ie: enable function end-point 3 interrupt when the fe3 ie bit is set (1), the function end-point 3 interrupt is enabled. bit 3 ? hep0 ie: enable endpoint 0 interrupt when the hep0 ie bit is set (1), the hub endpoint 0 interrupt is enabled. bit 2 ? fep2 ie: enable endpoint 2 interrupt when the fe2 ie bit is set (1), the function endpoint 2 interrupt is enabled. bit 1 ? fep1 ie: enable endpoint 1 interrupt when the fe1 ie bit is set (1), the function endpoint 1 interrupt is enabled. bit 0 ? fep0 ie: enable endpoint 0 interrupt when the fe0 ie bit is set (1), the function endpoint 0 interrupt is enabled. bit 7 6 5 4 3 2 1 0 $1ff3 sof ie eof2 ie ? fep3 ie hep0 ie fep2 ie fep1 ie fep0 ie uier read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
36 3355c?usb?4/05 at43usb325 4.13.5 suspend/resume register ? sprsr bit 7 ? intd: external interrupt d the intd bit is set when an external interrupt at the intd pin is detected. bit 6 ? intc: external interrupt c the intc bit is set when an external interrupt at the intc pin is detected. bit 5 ? intb: external interrupt b the intb bit is set when an external interrupt at the intb pin is detected. bit 4 ? inta: external interrupt a the inta bit is set when an external interrupt at the inta pin is detected. note: inta/b/c/d cannot be used to wake up the at43usb325 from the suspend state. bit 3 ? bus int: usb bus interrupt when the usb reset separation feature is enabled (= sprsie and sprsmsk bits 3 are set to 1) the bus int bit is set when usb bus reset is detected by the usb hardware. bit 2 ? frwup: function remote wakeup the usb hardware sets this bit to signal that a key depression is detected indicating remote wakeup. an interrupt is generated if the frwup ie bit of the sprsie register is set. bit 1 ? rsm: resume the usb hardware sets this bit when a usb resu me signaling is detected at any of its port except port 1. an interrupt is generated if the rsm ie bit of the sprsie register is set. bit 0 ? glb susp: global suspend the usb hardware sets this bit when a usb global suspend signaling is detected. an interrupt is generated if the glbsusp ie bit of the sprsie register is set. bit 7 6 5 4 3 2 1 0 $1ffa intd intc intb inta bus int frwup rsm glb susp sprsr read/write r r r r r/w r r r initial value 0 0 0 0 0 0 0 0
37 3355c?usb?4/05 at43usb325 4.13.6 suspend/resume interrupt enable register ? sprsie bit 7 ? intd en: external interrupt d enable setting the intd en bit will initia te an interrupt wh enever the intd bit of sprsr is set. bit 6 ? intc en: external interrupt c enable setting the intc en bit will initia te an interrupt wh enever the intc bit of sprsr is set. bit 5 ? intb en: external interrupt b enable setting the intd en bit will initia te an interrupt wh enever the intb bit of sprsr is set. bit 4 ? inta en: external interrupt a enable setting the intd en bit will initia te an interrupt wh enever the inta bit of sprsr is set. bit 3 ? bus int en: usb reset interrupt enable when the bus int en bit is set, the usb and c resets are separated. a usb bus reset (se0 for longer than 3 ms) will reset the usb hardware only and not the c. ho wever, an interrupt to the c will be generated and bit 3 of sprsr is set. bit 2 ? frwup ie: function remote wakeup interrupt enable setting the frwup ie bit will initia te an interrupt whenever th e frwup bit of sprsr is set. bit 1 ? rsm ie: resume interrupt enable setting the rsm ie bit will initiate an interrupt whenever the rsm bit of sprsr is set. bit 0 ? glb susp ie: global suspend interrupt enable setting the glb susp ie bit will initiate an in terrupt whenever the glb susp bit of sprsr is set. bit 7 6 5 4 3 2 1 0 $1ff9 intd en intc en intb en inta en bus int en frwup ie rsm ie glb susp ie sprsie read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
38 3355c?usb?4/05 at43usb325 4.13.7 suspend/resume interrupt mask register ? sprsmsk the bits of the suspend/resume mask register are used to make an interrupt caused by an event in the suspend/resume register visible to the c. the suspend/resume interrupt enable register bits enables the interrupt while the suspend/resume interrupt mask register allows the c to control when it wants visibilit y to an interrupt. 1 = enable mask, 0 = disable mask. bit 7 ? intd msk: external interrupt d mask bit 6 ? intc msk: external interrupt c mask bit 5 ? intb msk: external interrupt b mask bit 4 ? inta msk: external interrupt a mask bit 3 ? bus int msk: usb reset interrupt mask bit 2 ? frwup msk: function remote wakeup interrupt mask bit 1 ? rsm msk: resume interrupt mask bit 0 ? glb susp msk: global suspend interrupt enable bit 7 6 5 4 3 2 1 0 $1ff8 intd msk intc msk intb msk inta msk bus int msk frwup msk rsm msk glb susp msk sprsmsk read/write w w w w w w w w initial value 0 0 0 0 0 0 0 0
39 3355c?usb?4/05 at43usb325 4.13.8 inta/b/c/d interrupt sense control register ? iscr bit 7,6 ? isc71, isc70: external interrupt d sense control bits isc71 and isc70 controls the level and sense of the input at the intd pin as defined below: isc71 isc70 description 0 0 low level of intd 0 1 reserved 1 0 falling edge of intd 1 1 rising edge of intd bit 5,4 ? isc61, isc60: external interrupt c sense control bits isc71 and isc70 controls the level and sense of the input at the intc pin as defined below: isc61 isc60 description 0 0 low level of intc 0 1 reserved 1 0 falling edge of intc 1 1 rising edge of intc bit 3,2 ? isc51, isc40: external interrupt b sense control bits isc51 and isc50 controls the level and sense of the input at the intb pin as defined below: isc51 isc50 description 0 0 low level of intb 0 1 reserved 1 0 falling edge of intb 1 1 rising edge of intb bit 1,0 ? isc41, isc40: external interrupt a sense control bits isc41 and isc40 controls the level and sense of the input at the inta pin as defined below: isc41 isc40 description 0 0 low level of inta 0 1 reserved 1 0 falling edge of inta 1 1 rising edge of inta bit 7 6 5 4 3 2 1 0 $1ff1 isc71 isc70 isc61 isc60 isc51 isc50 isc41 isc40 iscr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
40 3355c?usb?4/05 at43usb325 5. avr register set 5.1 status register and stack pointer 5.1.1 status register ? sreg bit 7 ? i: global interrupt enable the global interrupt enable bit must be set (one) for the interrupts to be enabled. the individual interrupt enable control is then performed in separate control registers. if the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. the i-bit is cleared by the hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (bit store) use the t bit as source and desti- nation for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. bit 5 ? h: half carry flag the half carry flag h indicates a half carry in some arithmetic operations. see the instruction set description for de tailed information. bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between the negative flag n and the two's complement over- flow flag v. see the instruction set description for detailed information. bit 3 ? v: two's complement overflow flag the two's complement overflow flag v supports two's complement arithmetics. see the instruc- tion set description for detailed information. bit 2 ? n: negative flag the negative flag n indicates a negative result after the different arithmetic and logic operations. see the instruction set description for detailed information. bit 1 ? z: zero flag the zero flag z indicates a zero result after the different arithmetic and logic operations. see the instruction set descriptio n for detailed information. bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see the instruction set description for de tailed information. note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. this must be handled by software. bit 7 6 5 4 3 2 1 0 $3f ($5f) i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
41 3355c?usb?4/05 at43usb325 5.1.2 stack pointer register ? sp the stack pointer points to the data sram stack area where the subroutine and interrupt stacks are located. this stack space in the data sram must be defined by the program before any subroutine calls are executed or interrupts are enabled. the stack pointer must be set to point above $60. the stack pointer is decremented by one when data is pushed onto the stack with the push instruction, and it is decremented by two when an address is pushed onto the stack with subroutine calls and interrupts. the stack pointer is incremented by one when data is popped from the stack with the pop instruction and it is incremented by two when an address is popped from the stack with return from subroutine ret or return from interrupt reti. 5.2 sleep modes to enter the sleep modes, the se bit in m cucr must be set (one) and a sleep instruction must be executed. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu awakes, executes the interrupt routine, and resu mes execution from the instruction following sleep. the contents of the regist er file, sram and i/o memory are unaltered. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. 5.2.1 power down mode when the sm bit is set (one), the sleep instruction forces the mcu into the po wer down mode. in this mode, the external osc illator is stopped, while the exter nal interrupts c ontinue operating. only an external reset, an external level interrupt on int0 or int1, can wake up the mcu. note that when a level triggered interrupt is used for wake-up from power down, the low level must be held for a time longer than the reset delay time-out period t tout . otherwise, the mcu will fail to wake up. bit 1514131211109 8 $3e ($5e) ithsvnzcsph $3d ($5d) sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76 5 4 3210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 00 0 0 0000
42 3355c?usb?4/05 at43usb325 6. timer/counters the at43usb325 provides two general-purpose timer/counters - one 8-bit t/c and one 16-bit t/c. the timer/counters have individual prescali ng selection from the same 10-bit prescaling timer. both timer/counters can either be used as a timer with an internal clock time base or as a counter with an external pin connection which triggers the counting. 6.1 timer/counter prescaler the four different prescaled selections are: ck/8, ck/64, ck/256 and ck/1024 where ck is the oscillator clock. for the two time r/counters, added sele ctions as ck, extern al source and stop, can be selected as clock sources. figure 6-1. timer/counter prescaler 10-bit t/c prescaler cs00 cs01 cs02 cs10 cs11 cs12 0 0 ck t0 t1 ck/8 ck/64 ck/256 ck/1024 timer/counter1 clock source tck1 timer/counter0 clock source tck0
43 3355c?usb?4/05 at43usb325 6.2 8-bit timer/counter0 the 8-bit timer/counter0 can select clock source from ck, prescaled ck or an external pin. in addition it can be stopped as described in the specification for the timer/counter0 control reg- ister (tccr0). the overflow status flag is fou nd in the timer/counter interrupt flag register (tifr). control signals are found in the timer/counter0 control register (tccr0). the interrupt enable/disable settings for timer/counter0 are found in the timer/counter interrupt mask regis- ter - timsk. when timer/counte r0 is externally clocked, the external signal is synchronized with the oscilla- tor frequency of the cpu. to assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal cpu clock period. the external clock signal is sampled on the rising edge of the internal cpu clock. the 8-bit timer/counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportunities. similarly, th e high prescaling opportunities make the timer/counter0 useful for lower speed functions or exact timing functions with infrequent actions. figure 6-2. timer/counter0 block diagram control logic timer/counter0 (tcnt0) timer int. mask register (timsk) timer int. flag register (tifr) t/c0 control register (tccr0) toie1 oicie1a oicie1b ticie1 toie0 tov1 ocf1a ocf1b icf1 tov0 cs02 cs01 cs00 t/c clock source tov0 70 ck t0 t/c0 overflow irq 8-bit data bus
44 3355c?usb?4/05 at43usb325 6.2.1 timer/counter0 control register ? tccr0 bits 7..3 ? res: reserved bits these bits are reserved bits in the at43usb325 and always read as zero. bits 2, 1, 0 ? cs02, cs01, cs00: clock select0, bit 2, 1 and 0 the clock select0 bits 2, 1 and 0 define the prescaling source of timer/counter0. the stop condition provides a timer enable/disab le function. the ck down divided modes are scaled directly from the ck oscillator clock. if the external pin modes are used for timer/counter0, transitions on pb0/( t0) will clock the counter even if the pin is configured as an output. this feature can give the user sw control of the counting. 6.2.2 timer/counter0 ? tcnt0 the timer/counter0 is realized as an up-counter with read and write access. if the timer/counter0 is written and a clock source is present, the timer/counter0 continues counting in the clock cycle followin g the write operation. bit7654321 0 $33 ($53) ? ? ? ? ? cs02 cs01 cs00 tccr0 read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 6-1. clock 0 prescale select cs02 cs01 cs00 description 0 0 0 stop, the timer/counter0 is stopped 001ck 010ck/8 011ck/64 100ck/256 101ck/1024 1 1 0 external pin t0, falling edge 1 1 1 external pin t0, rising edge bit 76543210 $32 ($52) msb??????lsbtcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
45 3355c?usb?4/05 at43usb325 6.3 16-bit timer/counter1 figure 6-3. timer/counter1 block diagram control logic timer int. mask register (timsk) t/c1 control register a (tccr1a) t/c1 control register b (tccr1b) toie1 ocie1a ocie1b ticie1 toie0 com1a1 com1a0 com1b1 icf1 pwm11 cs12 cs11 cs10 ck t1 t/c1 overflow irq 8-bit data bus 7 0 t/c1 input capture register (icr1) 8 15 timer/counter1 (tcnt1) 16-bit comparator timer/counter1 output compare register a 16-bit comparator timer/counter1 output compare register b 7 0 8 15 7 0 8 15 7 0 8 15 0 15 7 0 8 15 7 8 t/c1 compare matcha irq t/c1 compare matchb irq t/c1input capture irq tov1 ocf1a ocf1b icf1 tov0 tov1 timer int. flag register (tifr) ctc1 icnc1 ices1 com1b0 ocf1a ocf1b pwm10 capture trigger
46 3355c?usb?4/05 at43usb325 6.4 16-bit timer/counter1 operation the 16-bit timer/counter1 can select clock source from ck, prescaled ck or an external pin. in addition, it can be stopped as described in the specification for the timer/counter1 control reg- isters (tccr1a and tccr1b). the different status flags (overflow, compare match and capture event) are found in the timer/counter interrupt flag register (tifr). control signals are found in the timer/counter1 control registers (tccr1a and tccr1b). the interrupt enable/disable settings for timer/counter1 are found in the timer/counter interrupt mask register (timsk). when timer/counte r1 is externally clocked, the external signal is synchronized with the oscilla- tor frequency of the cpu. to assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal cpu clock period. the external clock signal is sampled on the rising edge of the internal cpu clock. the 16-bit timer/counter1 features both a high resolution and a high accuracy usage with the lower prescaling opportunities. similarly, t he high prescaling opportunities makes the timer/counter1 useful for lower speed functions or exact timing functions with infrequent actions. the timer/counter1 supports two output comp are functions using the output compare regis- ter 1 a and b (ocr1a and ocr1b) as the data sources to be compared to the timer/counter1 contents. the output compare functions include optional clearing of the counter on comparea match, and actions on the output compare pins on both compare matches. timer/counter1 can also be used as a 8-, 9- or 10-bit pulse with modulator. in this mode the counter and the ocr1a/ocr1b registers serve as a dual glitch-free stand-alone pwm with centered pulses. the input capture function of timer/counter1 provides a capture of the timer/counter1 con- tents to the input capture register - icr1, tri ggered by an external event on the input capture pin (icp/pf3). the actual capture event settings are defined by the timer/counter1 control register (tccr1b). the at43usb325 has no anal og comparator and the mux control signal, aco, is permanently set so that the icp input is routed to the noise canceler. if the noise canceler function is enabled, the actual trigger condition for the capture event is monitored over 4 samples, and all 4 must be equal to activate the capture flag. figure 6-4. icp pin schematic diagram icp 0 1 noise canceler edge select icnc1 ices1 icf1 acic aco acic: comparator ic enable acc0: comparator output
47 3355c?usb?4/05 at43usb325 6.4.1 timer/counter1 cont rol register a ? tccr1a bits 7, 6 ? com1a1, com1a0: compare outp ut mode1a, bits 1 and 0 the com1a1 and com1a0 control bits determine any output pin action following a compare match in timer/counter1. any output pin actions affect pin oc1a (output comparea) pin 1. this is an alternative function to an i/o port and t he corresponding direction control bit must be set (one) to control the output pin. the control configuration is shown in table 6-2 . bits 5, 4 ? com1b1, com1b0: compare ou tput mode1b, bits 1 and 0 the com1b1 and com1b0 control bits determine any output pin action following a compare match in timer/counter1. any output pin actions affect pin oc1b (output compareb). the fol- lowing control configuration is given: note: 1. x = a or b 2. in pwm mode, these bits have a different function. refer to table 6-6 for a detailed description. bits 3..2 ? res: reserved bits these bits are reserved bits in the at43usb325 and always read zero. bits 1..0 ? pwm11, pwm10: pulse width modulator select bits 1 and 0 these bits select pwm operation of timer/counter1 as specified in table 6-3 . bit 7 6543210 $2f ($4f) com1a1 com1a0 com1b1 com1b0 ? ? pwm11 pwm10 tccr1a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 6-2. compare 1 mode select (2) com1x1 com1x0 description 0 0 timer/counter1 disconnected from output pin oc1x. (1) 0 1 toggle the oc1x output line. (1) 1 0 clear the oc1x output line (to zero). (1) 1 1 set the oc1x output line (to one). (1) table 6-3. pwm mode select pwm11 pwm10 description 0 0 pwm operation of timer/counter1 is disabled. 0 1 timer/counter1 is an 8-bit pwm. 1 0 timer/counter1 is a 9-bit pwm. 1 1 timer/counter1 is a 10-bit pwm.
48 3355c?usb?4/05 at43usb325 6.4.2 timer/counter1 cont rol register b ? tccr1b bit 7 ? icnc1: input capture1 no ise canceler (4 cks) when the icnc1 bit is cleared (z ero), the input captur e trigger noise canceler function is dis- abled. the input capture is triggered at the first rising/falling edge sampled on the icp (input capture pin) as specified. when the icnc1 bit is set (one), four successive samples are mea- sured on the icp and all samples must be high/low according to the input capture trigger specification in the ices1 bit. the actual sampling frequency is the 12 mhz system clock frequency. bit 6 ? ices1: input capture1 edge select while the ices1 bit is cleared (zero), the timer/counter1 contents are transferred to the input capture register (icr1) on the falling edge of the icp. while the ices1 bit is set (one), the timer/counter1 contents are transferred to the icr1 on the rising edge of the icp. bits 5, 4 ? res: reserved bits these bits are reserved bits in the at43usb325 and always read zero. bit 3 ? ctc1: clear timer/counter1 on compare match when the ctc1 control bit is set (one), the time r/counter1 is reset to $0000 in the clock cycle after a comparea match. if the ctc1 control bit is cleared, timer/counter1 continues counting and is unaffected by a compare match. since the compare match is detected in the cpu clock cycle following the match, this f unction will behave differently when a prescaling higher than 1 is used for the timer. when a prescaling of 1 is used, and the comparea register is set to c, the timer will count as follo ws if ctc1 is set: ... | c-2 | c-1 | c | 0 | 1 | ... when the prescaler is set to divide by 8, the timer will count like this: ... | c-2, c-2, c-2, c-2, c-2, c-2, c-2, c-2 | c-1, c-1, c-1, c-1, c-1, c-1, c- 1, c-1 | c, 0, 0, 0, 0, 0, 0, 0 | ... in pwm mode, this bit has no effect. bits 2, 1, 0 ? cs12, cs11, cs10: clock select1, bit 2, 1 and 0 the clock select1 bits 2, 1 and 0 define the prescaling source of timer/counter1. bit 7 6543210 $2e ($4e) icnc1 ices1 ? ? ctc1 cs12 cs11 cs10 tccr1b read/write r/w r/w r /w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 6-4. clock 1 prescale select cs12 cs11 cs10 description 0 0 0 stop, the timer/counter1 is stopped. 001ck 010ck/8 011ck/64 100ck/256
49 3355c?usb?4/05 at43usb325 the stop condition provides a timer enable/disab le function. the ck down divided modes are scaled directly from the 12 mhz system clock. if the external pin modes are used for timer/counter1, transitions on pb1/( t1) will clock the counter even if the pin is configured as an output. this feature can give the user sw control of the counting. 6.4.3 timer/counter1 ? tcnt1h and tcnt1l this 16-bit register contains the prescaled value of the 16-bit timer/counter1. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary register (temp). this temporary reg- ister is also used when accessing ocr1a, ocr1b and icr1. if the main program and also interrupt routines perform access to registers using temp, interrupts must be disabled during access from the main program and from interrupt routines if interrupts are allowed from within interrupt routines. tcnt1 timer/counter1 write: when the cpu writes to the high byte tcnt1h, the written data is placed in the temp register. next, when the cpu writes the low byte tcnt1l, this byte of data is combined with the byte data in the temp register, and all 16 bits are written to the tcnt1 timer/counter1 register simultaneously. consequently, the high byte tcnt 1h must be accessed first for a full 16-bit reg- ister write operation. tcnt1 timer/counter1 read: when the cpu reads the low byte tcnt1l, the data of the low byte tcnt1l is sent to the cpu and the data of the high byte tcnt1h is placed in the temp register. when the cpu reads the data in the high byte tcnt1h, the cpu receives the data in the temp register. consequently, the low byte tcnt1l must be accessed first for a full 16-bit register read operation. the timer/counter1 is realized as an up or up/down (in pwm mode) counter with read and write access. if timer/counter1 is written to and a cl ock source is selected, the timer/counter1 con- tinues counting in the timer clock cycle after it is preset with the written value. 101ck/1024 1 1 0 external pin t1, falling edge 1 1 1 external pin t1, rising edge table 6-4. clock 1 prescale select (continued) cs12 cs11 cs10 description bit 15 14 13 12 11 10 9 8 $2d ($4d) msb ? ? ? ? ? ? ? tcnt1h $2c ($4c) ? ? ? ? ? ? ? lsb tcnt1l 76 5 4 3210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 00 0 0 0000
50 3355c?usb?4/05 at43usb325 6.4.4 timer/counter1 output compare register ? ocr1ah and ocr1al 6.4.5 timer/counter1 output compare register ? ocr1bh and ocr1bl the output compare registers are 16-bit read/write registers. the timer/counter1 output compare registers contain the data to be continuously compared with timer/counter1. actions on compare matche s are specified in the timer/counter1 control and status register.a compare match does only occur if timer/counter1 counts to the ocr value. a software write that sets tcnt1 and ocr1a or ocr1b to the same value does not gen- erate a compare match. a compare match will set the compar e interrupt flag in the cpu clock cycle following the com- pare event. since the output compare registers ocr1a and ocr1b are 16-bit registers, a temporary reg- ister temp is used when ocr1a/b are written to ensure that both bytes are updated simultaneously. when the cpu writes the high byte, ocr1ah or ocr1bh, the data is tempo- rarily stored in the temp register. when the cpu writes the low byte, ocr1al or ocr1bl, the temp register is simultaneously written to ocr1ah or ocr1bh. consequently, the high byte ocr1ah or ocr1bh must be written first for a full 16-bit register write operation. the temp register is also used when access ing tcnt1, and icr1. if the main program and also interrupt routines perform access to registers using temp, interrupts must be disabled dur- ing access from the main program and from interrupt routines if interrupts are allowed from within interrupt routines. bit 1514131211109 8 $2b ($4b) msb ? ? ? ? ? ? ? ocr1ah $2a ($4a) ? ? ? ? ? ? ? lsb ocr1al 76 5 4 3210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 00 0 0 0000 bit 1514131211109 8 $29 ($49) msb ? ? ? ? ? ? ? ocr1bh $28 ($48) ? ? ? ? ? ? ? lsb ocr1bl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 00000000
51 3355c?usb?4/05 at43usb325 6.4.6 timer/counter1 input capture register ? icr1h and icr1l the input capture register is a 16-bit read-only register. when the rising or falling edge (according to th e input capture edge setting - ices1) of the sig- nal at the input capture pin (icp) is detect ed, the current value of the timer/counter1 is transferred to the input capture register (icr1). at the same time, the input capture flag (icf1) is set (one). since the icr1 is a 16-bit register, a temporary register temp is used when icr1 is read to ensure that both bytes are read simultaneously. when the cpu reads the low byte icr1l, the data is sent to the cpu and the data of the high byte icr1h is placed in the temp register. when the cpu reads the data in the high byte icr1h, the cpu receives the data in the temp register. consequently, the low byte icr1l must be accessed first for a full 16-bit register read operation. the temp register is also used when accessi ng tcnt1, ocr1a and ocr1b. if the main pro- gram and also interrupt routines perform access to registers using temp, interrupts must be disabled during access from the main program and from interrupt routines, if interrupts are allowed from within interrupt routines. 6.4.7 timer/counter1 in pwm mode when the pwm mode is selected, timer/counter1, the output compare register1a (ocr1a) and the output compare register1b (ocr1b) form a dual 8-, 9- or 10-bit, free-running, glitch- free and phase correct pwm with outputs on the pd5 (oc1a) and oc1b pins. timer/counter1 acts as an up/down counter, counting up from $0000 to top (see table 6-5 ), where it turns and counts down again to zero before the cycle is repeated. when the counter value matches the contents of the 10 least significant bits of o cr1a or ocr1b, the pd5(oc1a)/oc1b pins are set or cleared according to the settings of the com1a1/com1a0 or com1b1/com1b0 bits in the timer/counter1 control re gister tccr1a. refer to table 6-6 for details. bit 1514131211109 8 $25 ($45) msb ? ? ? ? ? ? ? icr1h $24 ($44) ? ? ? ? ? ? ? lsb icr1l 76 5 4 3210 read/write r r r r r r r r rrrrrrrr initial value 0 0 0 0 0 0 0 0 00 0 0 0000 table 6-5. timer top values and pwm frequency pwm resolution timer top value frequency 8-bit $00ff (255) f tck1 /510 9-bit $01ff (511) f tck1 /1022 10-bit $03ff(1023) f tck1 /2046
52 3355c?usb?4/05 at43usb325 note: x = a or b note that in the pwm mode, the 10 least signi ficant ocr1a/ocr1b bits, when written, are transferred to a temporary location. they are latched when timer/counter1 reaches the value top. this prevents the occurrence of odd-length pwm pulses (glitches) in the event of an unsynchronized ocr1a/ocr1b write. see figure 6-5 for an example. figure 6-5. effects on unsynchronized ocr1 latching note: x = a or b during the time between the wr ite and the latch operation, a read from ocr1a or ocr1b will read the contents of the temporary location. this means that the most recently written value always will read out of ocr1a/b when the ocr1 contains $0000 or top, the output oc1a/oc1b is updated to low or high on the next compare match, according to the settings of com1a1/com1a0 or com1b1/com1b0. this is shown in table 6-7 . note: if the compare register contains the top value and the prescaler is not in use (cs12..cs10 = 001), the pwm output will not produ ce any pulse at all, because up-counting and down-counting values are reached simultaneously. when the prescaler is in use (cs12..cs10 = 001 or 000), the pwm output goes active when the counter reaches the top value, but the table 6-6. compare1 mode select in pwm mode com1x1 com1x0 effect on ocx1 0 0 not connected 0 1 not connected 10 cleared on compare match, up-counting. set on compare match, down-counting (non-inverted pwm). 11 cleared on compare match, down-cou nting. set on compare match, up-counting (inverted pwm). synchronized ocr1x latch pwm output oc1x counter value compare value pwm output oc1x counter value compare value unsynchronized ocr1x latch glitch compare value changes compare value changes
53 3355c?usb?4/05 at43usb325 down-counting compare match is not interpreted to be reached before the next time the counter reaches the top value, making a one-period pwm pulse. note: x = a or b in pwm mode, the timer overflow flag1, tov1 , is set when the counter advances from $0000. timer overflow interrupt1 operates exactly as in normal timer/counter mode, i.e. it is executed when tov1 is set provided that timer overflow interrupt1 and global interrupts are enabled. this also applies to the timer output compare1 flags and interrupts. 6.5 watchdog timer the watchdog timer is clocked from a 1 mhz cl ock derived from the 6 mhz on chip oscillator. by controlling the watchdog timer prescaler, the watchdog reset interval can be adjusted, see table 6-8 for a detailed description. the wdr (watchdog reset) instruction resets the watch- dog timer. eight different clock cycle periods can be selected to determ ine the reset period. if the reset period expires without another watchdog reset, the at43usb325 resets and executes from the reset vector. to prevent unintentional disabling of the watchdog, a special turn-off sequence must be followed when the watchdog is disabled. refer to the description of the watchdog timer control register for details. figure 6-6. watchdog timer table 6-7. pwm outputs ocr1x = $0000 or top com1x1 com1x0 ocr1x output oc1x 1 0 $0000 l 10top h 1 1 $0000 h 11top l osc/16k osc/32k osc/64k osc/128k osc/256k osc/512k osc/1024k 1 mhz clock mcu reset wde wdp2 wdp1 wdp0 watchdog reset watchdog prescaler osc/8k
54 3355c?usb?4/05 at43usb325 6.5.1 watch dog timer control register ? wdtcr bits 7..5 ? res: reserved bits these bits are reserved bits in the at 43usb325 and will always read as zero. bit 4 ? wdtoe: watch dog turn-off enable this bit must be set (one) when the wde bit is cleared. otherwise, th e watchdog will not be dis- abled. once set, the ha rdware will clear this bit to zero a fter four clock cycl es. refer to the description of the wde bit for a watchdog disable procedure. bit 3 ? wde: watch dog enable when the wde is set (one) the watchdog timer is enabled, and if the wde is cleared (zero) the watchdog timer function is disabled. wde can only be cleared if the wdtoe bit is set (one). to disable an enabled watchdog timer, the following procedure must be followed: 1. in the same operation, write a logical one to wdtoe and wde. a logical one must be written to wde even though it is set to one before the disable operation starts. 2. within the next four clock cycles, write a logical 0 to wde. this disables the watchdog. bits 2..0 ? wdp2, wdp1, wdp0: watch dog timer prescaler 2, 1 and 0 the wdp2, wdp1 and wdp0 bits determine the watchdog timer prescaling when the watch- dog timer is enabled. the different prescaling va lues and their corresponding time-out periods are shown in table 6-8 . note: the wdr (watchdog reset) instruction should always be executed before the watchdog timer is enabled. this ensures that the reset period will be in accordance with the watchdog timer pres- cale settings. if the watchdog timer is enabled without reset, the watchdog timer may not start to count from zero. to avoid unintentional mcu re set, the watchdog timer should be disabled or reset before changing the watchdog timer prescale select. bit 7 6 5 4 3 2 1 0 $21 ($41) ? ? ? wdtoe wde wdp2 wdp1 wdp0 wdtcr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 6-8. watchdog timer prescale select wdp2 wdp1 wdp0 number of wdt oscillator cycles time-out 0 0 0 8k cycles 8.2 ms 0 0 1 16k cycles 16.4 ms 0 1 0 32k cycles 33.8 ms 0 1 1 64k cycles 65.6 ms 1 0 0 128k cycles 0.131 s 1 0 1 256k cycles 0.262 s 1 1 0 512k cycles 0.524 s 1 1 1 1,024k cycles 1.048 s
55 3355c?usb?4/05 at43usb325 7. i/o ports all gpio ports have true read-modify-write functionality when used as general digital i/o ports. this means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the sbi and cbi instructions. the same applies for changing drive value if configured as output or enabling/disabling of pull-up resistors if configured as input. the keyboard matrix strobe output pins, pa[0:7], pb[0:7] and pe[0:3] have controlled slope driv- ers. with a load of 100 pf, the output fall time ranges between 75 ns and 300 ns. the keyboard matrix strobe input pins, pc[0:7] have when the fe 3 imsk bit is set (1), the function end-point 3 interrupt is masked. pe[4:7] have 5v tolerant outputs and each has a built-in series resistor of 330 ? nominal value. these output pins are designed for driv ing an led connected to the 5v supply. the dedicated functions are summarized in table 7-1 . in the at43usb325e port f[0:3] are used as the spi sign als for the external serial eeprom. once the data from the seeprom are loaded to the sram, port f[1:3] become available as gpio pins. only cycling the power to the chip off and on again will temporarily assign these pins as eepom signals. table 7-1. gpio function assignments function gpio scan out[0:7] pa[0:7] scan out[8:15] pb[0:7] scan out[16:19] pe[0:3] scan in[0:7] pc[0:7] led drivers pe[4:7] eeprom interface pf[1:3]
56 3355c?usb?4/05 at43usb325 7.1 port a port a is an 8-bit bi-directional i/o port with open drain outputs and controlled slew rate. it is designed for use as the column driver in a keyboard controller. the port a output buffers can sink or source 4 ma. three i/o memory address locations are allocated for the port a, one each for the data register porta, $1b($3b), data direction register (ddra), $1a($3a) and the port a input pins (pina) $19($39). the port a input pins address is read only, while the data register and the data direction register are read/write. 7.1.1 port a data register ? porta 7.1.2 port a data direction register ? ddra 7.1.3 port a input pins address ? pina the port a input pins address (pina) is not a register, and this address enables access to the physical value on each port a pin. when reading porta the port a data latch is read, and when reading pina, the logical values present on the pins are read. bit 7 6 5 4 3 2 1 0 $1b ($3b) porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 porta read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $1a ($3a) dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7654 3 210 $19 ($39) pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 pina read/write r r r r r r r r initial value n/a n/a n/a n/a n/a n/a n/a n/a
57 3355c?usb?4/05 at43usb325 7.2 port b port b is an 8-bit bi-directional i/o port with open drain outputs and controlled slew rate. it is designed for use as the column driver in a keyboard controller. the port b output buffers can sink or source 4 ma. three i/o memory address locations are allocated for the port b, one each for the data register - portb, $18($38), data direction register (ddrb), $17($37) and the port b input pins (pinb), $16($36). the port b input pins address is read only, while the data register and the data direction register are read/write. 7.2.1 port b data register ? portb 7.2.2 port b data direction register ? ddrb 7.2.3 port b input pins address ? pinb the port b input pins address (pinb) is not a register, and this address enables access to the physical value on each port b pin. when reading portb, the port b data latch is read, and when reading pinb, the logical values present on the pins are read. bit 7 6 5 4 3 2 1 0 $18 ($38) portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $17 ($37) ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $16 ($36) pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 pinb read/write r r r r r r r r initial value n/a n/a n/a n/a n/a n/a n/a n/a
58 3355c?usb?4/05 at43usb325 7.3 port c port c is an 8-bit bi-directional i/o port with an internal pull-up resistor at each pin. port c is designed for use as the row inputs of a keyboard controller. its output buffers can sink 4 ma. three i/o memory address locations are allocated for the port c, one each for the data register - portc, $15($35), data direction register - ddrc, $14($34) and the port c input pins ? pinc, $13($33). the port c input pin?s address is read only, while the data register and the data direction register are read/write. 7.3.1 port c data register ? portc 7.3.2 port c data direction register ? ddrc 7.3.3 port c input pins address ? pinc the port c input pins address (pinc) is not a register, and this address enables access to the physical value on each port c pin. when reading portc, the port c data latch is read, and when reading pinc, the logical values present on the pins are read. bit 7 6 543210 $15 ($35) portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 portc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $14 ($34) ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 543210 $13 ($33) pinc7 pinc6 pinc5 pinc4 pi nc3 pinc2 pinc1 pinc0 pinc read/write r r r r r r r r initial value n/a n/a n/a n/a n/a n/a n/a n/a
59 3355c?usb?4/05 at43usb325 7.4 port d port d is a 7-bit bi-directional i/o port. three i/o memory address locations are allocated for the port d, one each for the data register - portd, $12($32), data directi on register - ddrd, $11($31) and the port d input pins - pind, $10($30). the port d input pins address is read only, while the data register and the data direction register are read/write. some po rt d pins have alternate functions as shown in the following table: when the pins are used for the alternate function the ddrd and portd register has to be set according to the alternate function description. 7.4.1 port d data register ? portd 7.4.2 port d data direction register ? ddrd 7.4.3 port d input pins address ? pind the port d input pins address (pind) is not a register, and this address enables access to the physical value on each port d pin. when reading portd, the port d data latch is read, and when reading pind, the logical values present on the pins are read. table 7-2. port d pins alternate functions port pin alternate function pd1 t1 (timer/counter1 ex ternal counter input) pd3 int1 (external interrupt 1 input) pd4 inta (external interrupt a input) pd5 intb (external interrupt b input) pd6 intc (external interrupt c input) pd7 intd (external interrupt d input) bit 7 6 5 4 3 2 1 0 $12 ($32) portd7 portd6 portd5 portd4 portd3 ? portd1 portd0 portd read/write r/w r/w r/w r/w r/w ? r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $11 ($31) ddd7 ddd6 ddd5 ddd4 ddd3 ? ddd1 ddd0 ddrd read/write r/w r/w r/w r/w r/w ? r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $10 ($30) pind7 pind6 pind5 pind4 pind3 ? pind1 pind0 pind read/write r r r r r ? r r initial value n/a n/a n/a n/a n/a n/a n/a n/a
60 3355c?usb?4/05 at43usb325 7.4.4 port d as general digital i/o pdn, general i/o pin: the dddn bit in the ddrd register selects the direction of this pin. if dddn is set (one), pdn is con-fi gured as an outp ut pin. if dddn is cleared (zero), pdn is config- ured as an input pin. the value of portdn has no meaning in this mode. the port d pins are tri-stated when a reset condition becomes active. note: n: 7,6,5,4,3,1,0, pin number 7.4.5 alternate functions of port d int1, external interrupt source 1: the pd3 pin can serve as an external interrupt source to the mcu. see the interrupt description for further details, and how to enable the source. 7.5 port e port e[0:3] each is a bi-directional i/o port with open drain outputs and controlled slew rate and is designed for use as the column drivers in a keyboard controller. the port e[0:3] output buffers can sink 4 ma. port e[4:7] are bi-directional i/o with outputs capable of driving leds directly. each pin of port e[4:7] has a series resistor to limit the leds current. three i/o memory address locations are allocated for the port e, one each for the data register - porte, $03($23), data direction register - ddre, $02($22) and the port e input pins - pine, $01($21). the port e input pins address is read only, while the data register and the data direction register are read/write. 7.5.1 port e data register ? porte 7.5.2 port e data direction register ? ddre table 7-3. dddn bits on port d pins dddn portdn i/o comment 0 0 input tri-state (hi-z) 0 1 input tri-state (hi-z) 1 0 output push-pull zero output 1 1 output push-pull one output bit 7 6 5 4 3 2 1 0 $03($23) porte7 porte6 porte5 porte4 porte3 porte2 porte1 porte0 porte read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $02 ($22) dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 ddre read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
61 3355c?usb?4/05 at43usb325 7.5.3 port e input pins address ? pine the port e input pins address, pine, is not a register, and this address enables access to the physical value on each port e pin. when reading porte the port e data latch is read, and when reading pine, the logical values present on the pins are read. 7.5.4 port e as general digital i/o pen, general i/o pin: the dden bit in the ddre register selects the direction of this pin. if dden is set (one), pen is con-figured as an output pin. if dden is cleared (zero), pen is config- ured as an input pin. the value of porten has no meaning in this mode. the port e pins are tri- stated when a reset condition becomes active. note: n: 7,6?0, pin number 7.6 port f port f[1:3] is a 3-bit bi-directional i/o that bec omes available after the program memory is writ- ten at the end of por. three i/o memory address locations are allocated for the port f, one each for the data register - portf, $06($26), data direction register - ddrf, $05($25) and the port f input pins - pind, $04($24). the port f input pins address is read only, while the data register and the data direction register are read/write. some port f pins have alternate functions as shown in the following table: after power up, pf[1:3] are used to load the program memory. this process is automatic. after completion of program memory downloading, the ssn pin is de-asserted (=logic 1) and the pins functions as gpios. when the pins are used for the alternat e function, after downloading is completed, the ddrf and portf register has to be set according to the alternate function description. bit 7 6 5 4 3 2 1 0 $01 ($21) pine7 pine6 pine5 pine4 pine3 pine2 pine1 pine0 pine read/write r/w r/w r/w r/w r/w r/w r r initial value n/a n/a n/a n/a n/a n/a n/a n/a table 7-4. dden bits on port e pins dden porten i/o comment 0 0 input tri-state (hi-z) 0 1 input tri-state (hi-z) 1 0 output push-pull zero output 1 1 output push-pull one output table 7-5. port f pins alternate functions port pin alternate function 1 alternate function 2 pf1 sck (spi bus serial clock) oc1a (timer/counter1 output comparea match output) pf2 mosi (spi bus master output/slave input) oc1b (timer/counter1 output compareb match output) pf3 miso (spi bus master input/slave ou tput) icp (timer/cou nter1 input capture)
62 3355c?usb?4/05 at43usb325 7.6.1 port f data register ? portf 7.6.2 port f data direction register ? ddrf 7.6.3 port f input pin address ? pinf the port f input pins address - pinf - is not a register, and this address enables access to the physical value on each port f pin. when reading portf, the port f data latch is read, and when reading pinf, the logical values present on the pins are read. 7.6.4 port f as general digital i/o pfn, general i/o pin: after firmware downloading, the ddfn bit in the ddrf register selects the direction of this pin. if ddfn is set (one), pfn is con-figured as an output pin. if ddfn is cleared (zero), pfn is configured as an input pin. the value of portfn has no meaning in this mode. the port f pins are tri-stated when a reset condition becomes active. note: n: 3,2,1, pin number bit 7 6 5 4 3 2 1 0 $06($26) - - - - portf3 portf2 portf1 - portf read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $05($25) - - - - ddf3 ddf2 ddf1 - ddrf read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $04($24) - - - - pinf3 pinf2 pinf1 - pinf read/write r r r r r r r r initial value n/a n/a n/a n/a n/a n/a n/a n/a table 7-6. ddfn bits on port f pins ddfn portfn i/o comment 0 0 input tri-state (hi-z) 0 1 input tri-state (hi-z) 1 0 output push-pull zero output 1 1 output push-pull one output
63 3355c?usb?4/05 at43usb325 8. programming the usb module the usb hardware consists of two devices, hub and function, each with their own device address and endpoints. its operation is controlled through a set of memory mapped registers. the exact configuration of the usb device is de fined by the software and it can be programmed to operate as a compound device, or as a hub only or as a function only. the hub has the required control and interrupt endpoints. the number of external downstream ports is program- mable from 0 to 2. the dp and dm pins of the unused port(s) must be connected to ground. the usb function has one control endpoint and 2 programmable endpoints. all the endpoints have their own 8-byte fifos. if the hub is disabl ed, one extra endpoint becomes available to the function. 8.1 usb function the usb function hardware is designed to operate in the single packet mode and to manage the usb protocol layer. it consists of a serial inte rface engine (sie), endpoint fifos and a function interface unit (fiu). the sie performs the following tasks: usb si gnaling detection/generation, data serialization/de-serialization, data encoding/decoding, bit stuffing and un-stuffing, clock/data separation, and crc generation/checking. it also decodes and manages all packet data types and packet fields. the endpoint fifo buffers the data to be sent out or data received. the fiu manages the flow of data between the sie, fifo and the internal microcontroller bus. it controls the fifo and moni- tors the status of the transactions and interfaces to the cpu. it initiates interrupts and acts upon commands sent by the firmware. the usb function hardware of the at43usb325 ma kes the physical interface and the protocol layer transparent to the user. to start the proces s, the firmware must first enable the endpoints and which place them in receive mode by default. the device address by default is address 0. the usb function hardware then waits for a setup token from the host. when a valid setup token is received, it automatically stores the data packet in endpoint 0 fifo and responds with an ack. it then notifies the microcontroller through an interrupt. the microcontroller reads the fifo and parses the request. transactions for the non-control endpoints are even simpler. once the endpoint is enabled, it waits for an in or an out token depending whether it is programmed as an in or out endpoint. for example, if it is an in endpoint, the microcontroller simply loads the data into the endpoint's fifo and sets a bit in the control and status register. the usb hardwa re will assemble the data in a usb packet and waits for an in token. when it receives one, it automatically responds by transmitting the data packet and completes the transaction by waiting for the host's ack. when one is received, the usb hardware will signal t he microcontroller that the transaction has been completed successfully. retries and data toggles are performed automatically by the usb hard- ware. when the in endpoint is not ready to send data, in the case where the microcontroller has not filled the fifo, it will auto matically respond with a nak. similarly, an out endpoint will wait for an out token. when one is received, it will store the data in the fifo, completes the transaction and interrupt the microcontroller, which then reads the fifo and enables the endpoint for the next packet. if the fifo is not cleared, the usb hard- ware will responds with a nak. a detailed description of how usb transactions are handled is described in the following sec- tions. first for a control endpoint and then for non-control endpoints.
64 3355c?usb?4/05 at43usb325 8.1.1 control transfers at control end-point ep0 the description given below is for the function control end-point, but applies to the hub control end-point as well if the proper registers are used. the following illustration describes the three possible types of c ontrol transfers ? control write, control read and no-data control: the following state diagram shows how the vari ous state transitions are triggered. additional decision making may take place within the response states to determine the next expected state. unmarked arcs represent transitions that trigger immediately following completion of the response state processing. stable states, those requiring an interrupt to exit having no unmarked arcs as exit paths, are shown in bold. setup data status stage stage stage control write data0 data1 data0 data0/1 data1(0) control read data0 data1 data0 data0/1 data1(0) setup status stage stage no-data control data0 data1(0) setup(0) setup(0) out(1) out(0) out(0/1) ? in(1) in(1) setup(0) in(1) in(1) out(1) in(0) in(0/1) ? legend: datan data packet with pid?s data toggle bit equal to n data1(0) zero length data1 packet
65 3355c?usb?4/05 at43usb325 the following information describes how the at43usb325?s usb hardware and firmware oper- ates during a control transfer between the host and the hub?s or function?s control end-point. 8.1.2 idle state this is the default state from power-up. legend: data1/data0 = data packet with data1 or data2 pid data1(0) = zero length data1 packet idle setup response no-data status response control read status response control write status response rx_setup_int rx_out_int tx_complete_int tx_complete_int tx_complete_int rx_out_int control read data response tx_complete_int control write data response rx_out_int ( any stable state )
66 3355c?usb?4/05 at43usb325 8.1.3 setup response state the function interface unit (fiu) receives a setup token with 8 bytes of data from the host. the fiu stores the data in the fifo, sends an ack back to the host and asserts an rx_setup interrupt. hardware firmware 1. setup token, data from host 2. ack to host 3. store data in fifo 4. set rx setup int 5. read uisr 6. read csr0 7. read byte count 8. read fifo 9. parse command data 10. write to h/fcar0: 11. if control read: set dir, clear rx setup, fill fifo, set tx packet ready in car0 12. if control write: clear dir in car0 13. if no data stage: set data end, clear dir, set force stall in car0 14. set uiar[ep0 intack] to clear the interrupt source
67 3355c?usb?4/05 at43usb325 8.1.4 no-data status response state the function interface unit receives an in token from the host. the fiu responds with a zero length data1 packet until receiving an ack from the host, then asserts a tx_complete interrupt. 8.1.5 control read data response state the function interface unit receives an in token from the host. the fiu responds with naks until tx_packet_ready is set. the fiu then sends the data in the fifo upstream, retrying until it successfully receives an ack from the host. finally, the fiu clears the tx_packet_ready bit and assert s a tx_complete interrupt. hardware firmware 1. in token from host 2. send data1(0) 3. ack from host 4. set tx complete int 5. read uisr 6. read csr0 7. if set address, program the new address, set add_en bit 8. clear tx_complete, clear data end, set force stall in car0 9. set uiar[ep0 intack] hardware firmware 1. in token from host 2. a. if tx packet ready = 1, send data0/data1 b. if tx packet ready = 0, send nak 3. ack from host 4. clear tx packet ready set tx complete int 5. read uisr 6. read csr0 7. clear tx complete in car0: a. if more data: fill fifo, set tx packet ready, set dir in car0 b. if no more data: set force stall, set data end in car0 8. set uiar[ep0 intack] to clear interrupt source repeat steps 1 through 8
68 3355c?usb?4/05 at43usb325 8.1.6 control read status response state the function interface unit receives an out token from the host with a zero length data1 packet. the fiu responds with a nak until tx _complete is cleared. the fiu will then ack the retried out token from the host and assert an rx_out interrupt. 8.1.7 control write data response state the function interface unit receives an out token from the host with a data packet. the fiu places the incoming data into the fifo, iss ues an ack to the host, and asserts an rx_out interrupt. hardware firmware 1. out token from host 2. data1(0) from host 3. tx complete = 0 ? a. if yes, ack to host set rx out int b. if no, nak to host 4. read uisr 5. read csr0 6. clear rx out, set data end, set force stall in h/fcar0. note: a setup token will clear data end, therefore, it is not cleared by fw in case host retries. 7. set uiar[ep0 intack] to clear interrupt source hardware firmware 1. out token from host 2. put data0/data1 into fifo 3. ack to host 4. set rx out int 5. read uisr 6. read csr0 7. read fifo 8. clear rx out if last data packet, set force stall, set data end. 9. set uiar[ep0 intack] to clear the interrupt source repeat steps 1 through 9 until last data packet:
69 3355c?usb?4/05 at43usb325 8.1.8 control write status response state the function interface unit receives an in token from the host. the fiu responds with a zero length data1 packet, retrying until it receives an ack back from the host. the fiu then asserts a tx_complete interrupt. 8.1.9 interrupt/bulk in transfers at function end-point the firmware must first condition the end-point through the end-point control register, fend- p1/2/3_cntr: set end-point direction: set epdir set interrupt or bulk: eptype = 11 or 10 enable end-point: set epen the function interface unit receives an in token from the host. the fiu responds with naks until tx_packet_ready is set. the fiu then sends the data in the fifo upstream, retrying until it successfully receives an ack from the host. finally, the fiu clears the tx_packet_ready bit and assert s a tx_complete interrupt. 1. read uisr 2. read fcsr1/2/3 3. clear tx_complete if more data: fill fi fo, set tx packet ready wait for tx_complete interrupt if no more data: set data end in fcar1/2/3 4. set uiar[fep1/2/3 intack] to clear the interrupt source hardware firmware 1. in token from host 2. send data1(0) 3. ack from host 4. set tx complete int 5. read uisr 6. read csr0 7. clear tx complete, clear data end, set force stall in car0 8. set uiar[ep0 intack] to clear the interrupt source
70 3355c?usb?4/05 at43usb325 8.1.10 interrupt/bulk out transfers at function end-point ep1, 2 and 3 the firmware must first condition the end-point through the end-point control register, fend- p1/2/3_cntr: set end-point direction: clear epdir set interrupt or bulk: eptype = 11 or 10 enable end-point: set epen the function interface unit receives an out token from the host with a data packet. the fiu places the incoming data into the fifo, iss ues an ack to the host, and asserts an rx_out interrupt. 1. read uisr 2. read fcsr1/2/3 3. read fifo 4. clear rx_out if more data: wait for rx_out interrupt if no more data: set data end set uiar[fep1/2/3 intack] to clear the interrupt source
71 3355c?usb?4/05 at43usb325 8.2 usb registers the following sections describe the registers of the at43usb325?s usb hub and function units. reading a bit for which the micr ocontroller does not have read ac cess will yield a zero value result. writing to a bit for which the microcontroller does not have write access has no effect. 8.2.1 hub address register ? haddr the usb hub contains an address register that contains the hub address assigned by the host. this hub address register must be programmed by the microcontroller once it has received a set_address request from the host. the usb hardw are uses the new addre ss only after the status phase of the transaction is complet ed when the microcontroller has enabled the new address by setting bit 0 of the global state regist er. after power-up or reset, this register will contain the value of 0x00. 8.2.1.1 hub address register ? haddr bit 7 ? saen: single address enable the single address enable bit allows the microc ontroller to configure the at43usb325 into a single address or a composite device. once this capability is enabled, the hub endpoint 0 (hep0) is converted from a control endpoint to a programmable function endpoint fep3; all the endpoints would then operate on the single address. bit 6..0 ? hadd6...0: hub address[6:0] 8.2.2 function address register ? faddr the usb function contains an address register that contains the function address assigned by the host. this function address register must be programmed by the microcontroller once it has received a set_address request from the ho st and completed the status phase of the transaction. after power up or reset, this register will contain the value of 0x00. 8.2.2.1 function address register ? faddr bit 7 ? fen: function enable the function enable bit (fen) allows the firmwa re to enable or disable the function endpoints. the firmware will set this bit after receipt of a reset through t he hub, setportfea- ture[port_reset]. once this bit is set, the usb hardware pa sses to and fr om the host. when the single address bit is set, the condition of fen is ignored. bit 6..0 ? fadd6...0: function address[6:0] bit 7 6 5 4 3 2 1 0 $1fef saen hadd6 hadd5 hadd4 hadd3 hadd2 hadd1 hadd0 haddr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $1fee fen fadd6 fadd5 fadd4 fadd3 fadd2 fadd1 fadd0 faddr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
72 3355c?usb?4/05 at43usb325 8.3 endpoint registers 8.3.1 hub endpoint 0 control register ? hendp0_cr 8.3.2 function endpoint 0 control register ? fendp0_cr bit 7 ? epen: endpoint enable 0 = disable endpoint 1 = enable endpoint bit 6..4 ? reserved these bits are reserved in the at43usb325 and will read as zero. bit 3 ? dtgle: data toggle identifies data0 or data1 packets. this bit will automatically toggle a nd requires clearing by the firmware only in certain special circumstances. bit 2 ? epdir: endpoint direction 0 = out 1 = in bit 1, 0 ? eptype: endpoint type these bits must be programmed as 0, 0. bit 765432 1 0 $1fe7 epen ? ? ? dtgle epdir eptype1 eptype0 hendp0_cr $24 ($44) epen ? ? ? dtgle epdir eptype1 eptype0 fendp0_cr read/write r/w r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
73 3355c?usb?4/05 at43usb325 8.3.3 function endpoint 1-3 control register ? fendp1-3_cr bit 7 ? epen: endpoint enable 0 = disable endpoint 1 = enable endpoint bit 6..4 ? reserved these bits are reserved in the at43usb325 and will read as zero. bit 3 ? dtgle: data toggle identifies data0 or data1 packets. this bit will automatically toggle a nd requires clearing by the firmware only in certain special circumstances. bit 2 ? epdir: endpoint direction 0 = out 1 = in bit 1, 0 ? eptype: endpoint type these bits program the type of endpoint. bit 7 6 5 4 3 2 1 0 $1fe4 epen ? ? ? dtgle epdir eptype1 eptype0 fendp1_cr $1fe3 epen ? ? ? dtgle epdir eptype1 eptype0 fendp2_cr $1fe2 epen ? ? ? dtgle epdir eptype1 eptype0 fendp3_cr read/write r/w r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit1 bit0 type 0 1 isochronous 10bulk 1 1 interrupt
74 3355c?usb?4/05 at43usb325 8.3.4 hub endpoint 0 data register ? hdr0 8.3.5 function endpoint 0..3 data register ? fdr0..3 this register is used to read data from or to write data to the hub endpoint 0 fifo. bit 7..0 ? fdat7..0: fifo data hub endpoint 1 has a single byte data register instead of a fifo. this data register contains the hub and port status change bitmap. this data register is automatically updated by the usb hard- ware and is not accessible by th e firmware. the bits in this re gister when read by the host will be: bit 7,6 ? reserved these bits are reserved in the at43usb325 and will read as zero. bit 5 ? p5 sc: port 5 status change bit 4 ? p4 sc: port 4 status change bit 3 ? p3 sc: port 3 status change bit 2 ? p2 sc: port 2 status change bit 1 ? p1 sc: port 1 status change bit 0 ? h sc: hub status change bit 7 6 5 4 3 2 1 0 $1fd7 data7 data6 data5 data4 data3 data2 data1 data0 hdr0 $1fd5 data7 data6 data5 data4 data3 data2 data1 data0 fdr0 $1fd4 data7 data6 data5 data4 data3 data2 data1 data0 fdr1 $1fd3 data7 data6 data5 data4 data3 data2 data1 data0 fdr2 $1fd2 data7 data6 data5 data4 data3 data2 data1 data0 fdr3 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $ ? ? p5 cs p4 cs p3 sc p2 sc p1 sc h sc hdr1 read/write r/w r/w r/ w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
75 3355c?usb?4/05 at43usb325 8.3.6 hub endpoint 0 byte count register ? hbyte_cnt0 8.3.7 function endpoint 0..3 byte count register ? fbyte_cnt0..3 the contents of these registers stores the number of bytes to be sent or that was received by usb hub and function endpoints. this count includes the 16-bit crc. to get the actual byte count of the data, subtract the count in the register by 2. the maximum byte count supported by the at43usb325 is 8 bytes. hub endpoint 1 has no byte count register. bit 7..6 ? reserved these bits are reserved in the at43usb325 and will read as zero. bit 5..0 ? bytct5..0: byte count ? length of endpoint data packet bit 7654 3 210 hub ep0 $1fcf ? ? bytct5 bytct4 bytct3 bytct2 bytct1 bytct0 hbyte_cnt0 function ep0 $1fcd ? ? bytct5 bytct4 bytct3 bytct2 bytct1 bytct0 fbyte_cnt0 function ep1 $1fcc ? ? bytct5 bytct4 bytct3 bytct2 bytct1 bytct0 fbyte_cnt1 function ep2 $1fcb ? ? bytct5 bytct4 bytct3 bytct2 bytct1 bytct0 fbyte_cnt2 function ep3 $1fca ? ? bytct5 bytct4 bytct3 bytct2 bytct1 bytct0 fbyte_cnt3 read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
76 3355c?usb?4/05 at43usb325 8.3.8 hub endpoint 0 service routine register ? hcsr0 8.3.9 function endpoint 0 service routine register ? fcsr0 bit 7..4 ? reserved these bits are reserved in the at43usb325 and will read as zero. bit 3 ? stall sent the usb hardware sets this bit after a stall has been sent to the host. the firmware uses this bit when responding to a get status [endpoint] request. it is a r ead only bit and that is cleared indirectly by writing a one to the stall_sent_ack bit of the control and acknowledge register. bit 2 ? rx setup: setup packet received this bit is used by control endpoints only to signal to the microcontroller that the usb hardware has received a valid setup packet and that the data portion of the packet is stored in the fifo. the hardware will clear all other bits in this r egister while setting rx setup. if interrupt is enabled, the microcontroller will be interrupted when rx setup is set. after the completion of reading the data from the fifo, firmware should clear this bit by writing a one to the rx_setup_ack bit of the control and acknowledge register. bit 1 ? rx out packet the usb hardware sets this bit after it has stored the data of an out transaction in the fifo. while this bit is set, the hardware will nak a ll out tokens. the usb hardware will not overwrite the data in the fifo except for an early set-up. rx out packet is used for the following operations: 1. control write transactions by a control endpoint. 2. out transaction with data1 pid to complete the status phase of a control endpoint. setting this bit causes an interrupt to the microcontroller if the interrupt is enabled. fw clears this bit after the fifo contents have been read by writing a one to the rx_out_packet_ack bit of the control and acknowledge register. bit 0 ? tx compl: transmit completed this bit is used by a control endpoint hardware to signal to the microcontroller that it has suc- cessfully completed certain tr ansactions. tx complete is set at the completion of a: 1. control read data stage. 2. status stage without data stage. 3. status stage after a control write transaction. this bit is read only and is cleared indirectly by writing a one to the tx_complete_ack bit of the control and acknowledge register. bit 7 6 5 4 3 2 1 0 function ep0 $1fdf ? ? ? ? stall sent rx setup rx out packet tx complete hcsr0 function ep0 $1fdd ? ? ? ? stall sent rx setup rx out packet tx complete fcsr0 read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0
77 3355c?usb?4/05 at43usb325 8.3.10 hub endpoint 0 control and acknowledge register ? hcar0 8.3.11 function endpoint 0 control and acknowledge register ? fcar0 bit 7 ? dir: control transfer direction it is set by the microcontroller firmware to indi cate the direction of a control transfer to the usb hardware. the fw writes to this bit location after it receives an rx setup interrupt. the hard- ware uses this bit to determine the status phase of a control transfer. 0 = control write or no data stage 1 = control read bit 6 ? data end when set to 1 by firmware, this bit indicate t hat the microcontroller has either placed the last data packet in fifo, or that the microcontroller has processed the last data packet it expects from the host. this bit is used by control endpo ints only together with bit 4 (tx packet ready) to signal the usb hardware to go to the status phase after the packet currently residing in the fifo is transmitted. af ter the hardware completes the stat us phase it will in terrupt the micro- controller without clearing this bit. bit 5 ? force stall this bit is set by the microcontroller to indi cate a stalled endpoint. the hardware will send a stall handshake as a response to the next in or out token, or whenever there is a control transfer without a data stage. the microcontroller sets this bit if it wants to force a stall. a stall is sent if any of the follow- ing condition is encountered: 1. an unsupported request is received. 2. the host continues to ask for data after the data is exhausted. 3. the control transfer has no data stage. bit 4 ? tx packet ready: transmit packet ready when set by the firmware, this bit indicates that the microcontroller has loaded the fifo with a packet of data. this bit is cleared by the hard ware after the usb host acknowledges the packet. for iso endpoints, this bit is cleared unconditionally after the data is sent. this bit is used for the following operations: 1. control read transactions by a control endpoint. 2. in transactions with data1 pid to complete the status phase for a control endpoint, when this bit is zero but data end set high (bit 4). 3. by a bulk in or iso in or int in endpoint. bit 7 6 5 4 3 2 1 0 hub ep0 $1fa7 dir data end force stall tx packet ready stall_ sent_ ack rx_ setup_ ack rx_out_ packet_ ack tx_ complete_ ack hca r0 function ep0 $1fdd dir data end force stall tx packet ready stall_ sent_ ack rx_ setup_ ack rx_out_ packet_ ack tx_ complete_ ack fcar 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
78 3355c?usb?4/05 at43usb325 the microcontroller should write into the fifo only if this bit is cleared. after it has completed writing the data, it should set this bit. this data can be of zero length. hardware clears this bit after it receives an ack. if the interrupt is enabled and if the tx com- plete bit is set, clearing the tx packet ready bit by the hardware causes an interrupt to the microcontroller. bit 3 ? stall_sent_ack: acknowledge stall sent interrupt firmware sets this bit to clear stall sent, csr bit 3. the 1 written in the csrack3 bit is not actually stored and thus does not have to be cleared. bit 2 ? rx_setup_ack: acknowledge rx setup interrupt firmware sets this bit to clear rx setup, csr bit2. the 1 written in the csrack2 bit is not actually stored and thus does not have to be cleared. bit 1 ? rx_out_packet_ack: acknowledge rx out packet interrupt firmware sets this bit to clear rx out packet, csr bit1. the 1 written in the csrack1 bit is not actually stored and thus does not have to be cleared. bit 0 ? tx_complete_ack: acknowle dge tx complete interrupt firmware sets this bit to clear tx complete , csr bit0. the 1 written in the csrack0 bit is not actually stored and thus does not have to be cleared.
79 3355c?usb?4/05 at43usb325 8.3.12 function endpoint 1,2,3 service routine register ? fcsr1,2,3 bit 7..4 ? reserved these bits are reserved in the at43usb325 and will read as zero. bit 3 ? stall sent the usb hardware sets this bit after a stall has been sent to the host. the firmware uses this bit when responding to a get status [endpoint] request. it is a r ead only bit and that is cleared indirectly by writing a one to the stall_sent_ack bit of the control and acknowledge register. bit 2 ? reserved this bit is reserved in the at43usb325 and will read as zero. bit 1 ? rx out packet the usb hardware sets this bit after it has stored the data of an out transaction in the fifo. while this bit is set, the hardware will nak a ll out tokens. the usb hardware will not overwrite the data in the fifo except for an early set-up. rx out packet is used by a bulk out or iso out or int out endpoint. setting this bit causes an interrupt to the microcontroller if the interrupt is enabled. fw clears this bit after the fifo contents have been read by writing a one to the rx_setup_ack bit of the control and acknowledge register. bit 0 ? tx complete: transmit completed this bit is used by the endpoint hardware to sign al to the microcontroller that the in transaction was completed succe ssfully. this bit is read only and is clea red indirectly by writing a one to the tx_complete_ack bit of the control and acknowledge register. bit 7654 3 2 1 0 function ep1 $1fdc ????stall sent?rx out packettx completefcsr1 function ep2 $1fdb ????stall sent?rx out packettx completefcsr2 function ep3 $1fda ????stall sent?rx out packettx completefcsr3 read/write rrrr r r r r initial value 0000 0 0 0 0
80 3355c?usb?4/05 at43usb325 8.3.13 function endpoi nt 1,2,3 control and acknow ledge register ? fcar1,2,3 bit 7 ? reserved this bit is reserved in the at43usb325 and will read as zero. bit 6 ? data end when set to 1 by firmware, this bit indicate t hat the microcontroller has either placed the last data packet in fifo, or that the microcontroller has processed the last data packet it expects from the host. bit 5 ? force stall this bit is set by the microcontroller to indi cate a stalled endpoint. the hardware will send a stall handshake as a response to the next in or out token. the microcontroller sets this bit if it wants to force a stall. a stall is send if the host continues to ask for data after the data is exhausted. bit 4 ? tx packet rdy: transmit packet ready when set by the firmware, this bit indicates that the microcontroller has loaded the fifo with a packet of data. this bit is cleared by the hard ware after the usb host acknowledges the packet. for iso endpoints, this bit is cleared unconditionally after the data is sent. the microcontroller should write into the fifo only if this bit is cleared. after it has completed writing the data, it should set this bit. this data can be of zero length. the hardware clears this bit after it receives an ack. if the interrupt is enabled and if the tx complete bit is set, clearing the tx packet ready bit by the hardware causes an interrupt to the microcontroller. bit 3 ? stall_sent_ack: acknowledge stall sent interrupt firmware sets this bit to clear stall sent, csr bit 3. the 1 written in the csrack3 bit is not actually stored and thus does not have to be cleared. bit 2 ? reserved this bit is reserved in the at43usb325 and will read as zero. bit 1 ? rx_out_packet_ack: acknowledge rx out packet interrupt firmware sets this bit to clear rx out packet, csr bit1. the 1 written in the csrack1 bit is not actually stored and thus does not have to be cleared. bit 0 ? tx_complete_ack: acknowledge tx complete interrupt firmware sets this bit to clear tx complete , csr bit0. the 1 written in the csrack0 bit is not actually stored and thus does not have to be cleared. bit 7 6 5 4 3 2 1 0 function ep1 $1fa4 ? data end force stall tx packet rdy stall_sent -ack ? rx_out_packet _ack tx_complete _ack fcar1 function ep2 $1fa3 ? data end force stall tx packet rdy stall_sent -ack ? rx_out_packet _ack tx_complete _ack fcar2 function ep3 $1fa2 ? data end force stall tx packet rdy stall_sent -ack ? rx_out_packet _ack tx_complete _ack fcar3 read/write r r/w r/w r/w r/w r r/w r/w initial value 0 0 0 0 0 0 0 0
81 3355c?usb?4/05 at43usb325 8.4 usb hub the hub in a usb system provides for the elec trical interface between usb devices and the host. the major functions that the hub must supports are: connectivity power management device connect and disconnect bus fault detection and recovery full speed and low speed device support a hub consists of two major components: a hub repeater and a hub controller. the hub repeater is responsible for: providing upstream connectivity between the selected device and the host managing connectivity setup and tear-down handling bus fault detection and recovery detecting connect/disconnect on each port the hub controller is responsible for: hub enumeration providing configuration information to the host providing status of each port to the host controlling each port per host command the first two tasks of the hub are similar to that of a usb function and are described in detail in the following section. the descrip tions will cover the feat ures of the at43u sb325's hub and how to program it to make a usb-compliant hub. control transactions for the hub control endpoi nt proceed exactly the same way as those described for the embedded function. the operation of the hub's endpoint 1 is fully implemented in the hardware and does not ne ed any firmware supp ort. any status cha nges within the hub will automatically update hub end point 1, which will be sent to the ho st at the next in token that is addressed to it. if no change has occurred , the interrupt endpoint will respond with a nak.
82 3355c?usb?4/05 at43usb325 8.4.1 hub general registers 8.4.1.1 global state register ? glb_state bit 7 ? reserved bit this bit is reserved in the at43usb325 and will read as zero. bit 6 ? kb int en: keyboard interrupt enable the firmware must set this bit to a 1 before entering suspend to allow remote wakeup when any key depression is detected in the suspended state. bit 5 ? reserved bit this bit is reserved in the at43usb325 and will read as zero. bit 4 ? susp flg: suspend flag this bit is set to 1 while the us b hardware is in the suspended state. this bit is a firmware read only bit. it is set and cleared by the usb hardware. bit 3 ? resume flgl resume flag when the usb hardware receives a resume signal from the upstream device it sets this bit. this bit will stay set until the usb har dware completes the down stream resume signaling. this bit is a firmware read only bit. it is set and cleared by the usb hardware. bit 2 ? rmwupe: remote wakeup enable this bit is set if the host enables the hub's remote wakeup feature. bit 1 ? confg: configured this bit is set by firmware after a valid set_c onfiguration request is received. it is cleared by a reset or by a set_configuration with a value of 0. bit 0 ? hadd en: hub address enabled this bit is set by firmware a fter the status phase of a set_ad dress request transaction so the hub will use the new address starti ng at the next transaction. bit 7 6 5 4 3 2 1 0 $1ffb ? kb int en ? susp flg resume flg rmwupe confg hadd en glb_state read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0
83 3355c?usb?4/05 at43usb325 8.4.2 hub status register in the at43usb325 overcurrent detection and port power switch control output processing is done in firmware. the hardware is designed so that various types of hubs are possible just through firmware modifications. 1. hub local power status, bits 0 and 2, are optional features and apply to hubs that report on a global basis. if this feature is not used, both these bits should be programmed to 0. to use this feature, the firmware needs to know the status of the local power supply, which requires an input pin and extra internal or external circuitry. 2. hub overcurrent status, bits 1 and 3, apply to self powered hubs with bus powered sie only, or hubs that are programmable as self/bus powered. the firmware should clear these two bits to 0. the firmware uses bits 1 and 3 to generate bit 0 of the hub and port status change bitmap which is transmitted through the hub endpoint1 data register. bit 0 of this register is a 1 when- ever bit 1 or 3 of hstatr is a 1. 8.4.2.1 hub status register ? hstr bit 7..4 ? reserved these bits are reserved in the at43usb325 and will read as zero. bit 3 ? ovlsc: overcurrent status change 0 = no change has occurred on overcurrent indicator 1 = overcurrent indicator has changed bit 2 ? lpsc: hub local power status change 0 = no change has occurred on local power status 1 = local power status has changed bit 1 ? ovi: overcurrent indicator 0 = all power operations normal 1 = an overcurrent exist on a hub wide basis bit 0 ? lps: hub local power status 0 = local power supply is good 1 = local power supply is lost (inactive) bit76543210 $1fc7 ? ? ? ? ovlsc lpsc ovi lps hstr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
84 3355c?usb?4/05 at43usb325 8.4.2.2 hub port control register ? hpcon bit 7 ? reserved this bits is reserved in the at43usb325 and will read as zero. bit 6..4 ? hpcon2..0: hub port control command these bits are written by firmware to control the port states upon receipt of a host request. disable port = clearportfeature(port_enable) action: usb hardware places addressed port in disabled state. port 1 is placed in disabled state by firmware. enable port = setport feature(port_enable) action: usb hardware places addressed port in enabled state. firmware is responsible for plac- ing port 1 in enabled state. reset and enable port = setport feat ure(port_reset) action: usb hardware drives reset signaling through addressed port. usb hardware and firm- ware resets their embedded function registers to the default state. suspend port = setportfeatu re(port_suspend) action: usb hardware places port in idle state and stops propagating traffic through the addressed port. firmware places port 1 in suspend state by disabling its endpoints and placing the peripheral function in its low power state. resume port = clearportfeature(port_suspend) action: usb hardware sends resume signaling to addressed port and then enables port. firm- ware takes the embedded function out of the suspend state and enables port 1's endpoints. bit 3 ? reserved this bits is reserved in the at43usb325 and will read as zero. bit 2..0 ? hpcon2..0: hub port address bit76543210 $1fc5 ? hpcon2 hpcon1 hpcon0 ? hpadd2 hpadd1 hpadd0 hpcon read/write r r/w r/w r/w r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit6 bit5 bit4 action 0 0 0 disable port 0 0 1 enable port 0 1 0 reset and enable port 0 1 1 suspend port 1 0 0 resume port
85 3355c?usb?4/05 at43usb325 these bits define which port is being addressed for the command defined by bits [2:0]. 8.4.3 selective suspend and resume the host can selectively suspend and resume a port through the set port feature (port_suspend) and clear port feature (port_suspend). a port enters the suspend state after the microcontroller interprets the suspend request and sets the appropriate bits of the hub port contro l register, hpcon. from this point on he hub repeater hardware is responsible for proper actions in placing ports 2:5 in the suspend mode. for port 1, the embedded function port, the hardware will stop responding to any normal bus traffic, but the microcontroller firmware must place all external circuitry associated with the func- tion in the low-power state. a port exits from the suspend state when the hub receives a clear port feature (port_suspend) or set port feature (p ort_reset). if the clear port feature (port_suspend) is directed towards ports 2:5, the usb hardware drives a ?k? downstream for at least 20 ms followed by a low speed eop. it then places the port in the enabled state. a clear port feature (port_suspend) to port 1 (the embedded function) causes the firmware to wait 20 ms, take the embedded function out of the suspended state and then enable the port. the ports can also exit from the suspended state through a remote wakeup if this feature is enabled. for ports 2:5, this means detection of a connect/disconnect or an upstream directed j to k signaling. remote wakeup for the embedded function is initiated through a key depression which triggers a kb int. bit2 bit1 bit0 port addresses 101port5 100port4 011port3 010port2
86 3355c?usb?4/05 at43usb325 8.4.4 hub port status register the bits in this register are used by the microcontroller firmware when reporting a port's status through the port status field, wportstatus . bits 3 (poci) and 5 (ppstat) are used by the usb hardware and are the only two bits that the firm ware should set or clear. all other bits should not be modified by the firmware. 8.4.4.1 hub port status register ? hpstat1:5 bit 7 ? reserved this bit is reserved in the at43usb325 and will read as zero. bit 6 ? lsp: low-speed device attached 0 = full-speed device attached to this port 1 = slow-speed device attached to this port set to 0 for port 1 (full-speed only). set and cleared by the hardware upon detection of device at eof2. bit 5 ? ppstat: port power status 0 = port is powered off 1 = port is powered on set to 1 for port 1. set and cleared based on present status of port power. bit 4 ? prstat: port reset status 0 = reset signaling not asserted 1 = reset signaling asserted set and cleared by the hardware as a result of initiating a port reset by port control register. bit 3 ? poci: port overcurrent indicator 0 = power normal 1 = overcurrent exist on port set to 0 for port 1. set and cleared by firmware upon detection of an overcurrent or removal of an overcurrent. bit 7 6 5 4 3 2 1 0 port1 $1fb8 ? lsp ppstat prstat poci psstat pestat pcstat hpstat1 port2 $1fb9 ? lsp ppstat prstat poci psstat pestat pcstat hpstat2 port3 $1fba ? lsp ppstat prstat poci psstat pestat pcstat hpstat3 port4 $1fbb ? lsp ppstat prstat poci psstat pestat pcstat hpstat4 port5 $1fbc ? lsp ppstat prstat poci psstat pestat pcstat hpstat5 read/write r r r/w r r/w r r r initial value 0 0 0 0 0 0 0 0
87 3355c?usb?4/05 at43usb325 bit 2 ? psstat: port suspend status 0 = port not suspended 1 = port suspended set and cleared by the hardware as controlled through port control register. bit 1 ? pestat: port enable status 0 = port is disabled 1 = port is enabled set and cleared by the hardware as controlled through port control register. bit 0 ? pcstat: port connect status 0 = no device on this port 1 = device present on this port set to 1 for port 1. set and cleared by the hardware after sampling of connect status at eof2. 8.4.4.2 overcurrent detect register ? uovcer bit 7..3 ? reserved these bits are reserved in the at43usb325 and will read as zero. bit 2 ? ovc 2 setting this bit enables the hub to detect an overcurrent on a port while the hub is in the suspend state. the overcurrent condition is signalled by a 1 to 0 transition at pd0. bit 1, 0 ? reserved these bits are reserved in the at43usb325 and will read as zero. bit 7 6 5 4 3 2 1 0 $1ff2 ?? ? ? ?ovc2??uovcer read/write r r r r r r/w r r initial value 0 0 0 0 0 0 0 0
88 3355c?usb?4/05 at43usb325 8.4.4.3 hub port state register ? hpstat2...5 these registers contain the state of the ports? dp and dm pins, which will be sent to the host upon receipt of a getbusstate request. bit 7..2 ? reserved these bits are reserved in the at43usb325 and will read as zero. bit 1 ? dpstate: dplus state value of dp at last eof. set and cleared by hardware at eof2. set to 1 for port 1. bit 0 ? dmstate: dminus state value of dm at last eof. set and cleared by hardware at eof2. set to 0 for port 1. 8.4.4.4 hub port status change register ? pscr1..5 the microcontroller firmware uses the bits in th is register to monitor when a port status change has occurred, which then gets reported to the host through the port change field wportchange . except for bit 3, the port overcurrent indicator change, the bits in this register are set by the usb hardware. otherwise, the firmware should only clear these bits. bit 7..5 ? reserved these bits are reserved in the at43usb325 and will read as zero. bit 4 ? rstsc: port reset status change 0 = no change bit 7 6 5 4 3 2 1 0 port2 $1fa9 ? ? ? ? ? ? dpstate dmstate pstate2 port3 $1faa ? ? ? ? ? ? dpstate dmstate pstate3 port4 $1fab ? ? ? ? ? ? dpstate dmstate pstate4 port5 $1fac ? ? ? ? ? ? dpstate dmstate pstate5 read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 port1 $1fb0 ? ? ? rstsc pocic pssc pesc pcsc pscr1 port2 $1fb1 ? ? ? rstsc pocic pssc pesc pcsc pscr2 port3 $1fb2 ? ? ? rstsc pocic pssc pesc pcsc pscr3 port4 $1fb3 ? ? ? rstsc pocic pssc pesc pcsc pscr4 port5 $1fb4 ? ? ? rstsc pocic pssc pesc pcsc pscr5 read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0
89 3355c?usb?4/05 at43usb325 1 = reset complete this bit is set by the usb hardware after it completes reset signaling which is initiated when the reset and enable port command is detected at the port control register, hpcon. the firm- ware sends this command when it decodes a se tportfeature(port_reset) request from the host. at eof2 after the hardware completes the port reset, the hardware sets the port enable status bit and clears the port reset status bit of the hub port status register, hpstat. cleared by firmware, clearportf eature(port_reset). bit 3 ? pocic: port overcurrent indicator change 0 = no change has occurred on overcurrent indicator 1 = overcurrent indicator has changed this bit is relevant to hubs with individual overcurrent reporting only. the firmware sets this bit as a result of detecting overcurrent at the ports ovc# pin. the firmware clears bit through clear- portfeature(port_over_current). for port 1, this bit is always cleared. bit 2 ? pssc: port suspend status change 0 = no change 1 = resume completed port 2, 3 set by hardware upon completion of firmware initiated resume process. port 1 set by firmware 20 ms after the next eof2 after comple tion of resume process. resume signaling is initiated through global resume, selective resume and remote wakeup. cleared by firmware via host request clearport feature(port_suspend). bit 1 ? pesc: port enable/disable status change 0 = no change has occurred on port enable/disable status 1 = port enable/disable status has changed set by hardware due to babble, physical disconnect or overcurrent except for port 1 in which case it is set by hardware at eof2 due to hardware events. cleared by firmware via host request clearportfeature(port_enable). bit 0 ? pcsc: port connect status change 0 = no change has occurred on current connect status 1 = current connect status has changed this bit is set by hardware at eof2 after it detects a connect or disconnect at a port, except for port 1. hardware sets this bit for port 5 after a hub reset. cleared by firmware via host request clearportfeature(po rt_connection).
90 3355c?usb?4/05 at43usb325 8.4.5 hub and port power management overcurrent protection and power switching are required for the external downstream ports only. in the at43usb325, these tasks are completely programmable. this means that any type of hub is achievable with the at43usb325: self-powered or bus-powered hubs, per port or global overcurrent protection, individual or ganged port power switching. the use of the mcu's gpio pins are required to interface to the external power supply monitor- ing and switching. the on-chip hardware of the at 43usb325 contains the circuitry to handle all the possible combinations of port power man agement tasks. the firmware defines the exact configuration. 8.4.6 overcurrent sensing the at43usb325 is capable of detecting overcurrent during active operation only, or during any condition even when the hub is in the suspended state. when overcurrent in the active state only is desired, any gpio pin of the at43usb325 c an be used to sense and the overcurrent condi- tion. control of the condition must be performed by the firmware. if overcurrent detection under any condition is desired, then specific gpio pi ns must be used to sense the overcurrent and the proper bit(s) of uovcer set. in global over current protection mode, overcurrent sensing must be routed to gpio pd0. in individual port overcurrent protection mode port2 and port 3 over- current sensing must be assigned to gpio pd0 and pd1. in the following description, it is assumed that overcurrent protection is required under any condition. 1. global overcurrent protection ? in this mode, the port overcurrent indicator and port overcurrent indicator change should be set to 0's. for the at43usb325 an external solid state switch, such as the micrel mic2025-2, is required to switch power to the external usb ports. the flg output of the switch should be connected to pd0. when an overcurrent occurs, flg is asserted and the firmware should set the hub overcur- rent indicator and hub overcurrent indicator change and switch off power to all external downstream ports. the hub status change is reported on the next in token through the hub's interrupt endpoint, endpoint1. 2. individual port overcurrent protection ? the hub overcurrent indicator and hub overcurrent indicator change bits should be set to 0's. one mic2026-2 is required for the two usb ports. the flg output of the mic2026-2 associated with port2 should be connected to gpio pd0 and the other flg output to pd1. an overcurrent is indicated by assertion of flg. the firmware sets the corresponding port's overcurrent indicator and the overcurrent indicator change bits and switches off power to the port. at the next in token from the host, the at43usb325 reports the port status change through the hub's endpoint1. 8.4.7 port power switching 1. gang power switching ? one of the microcontroller gpio pins, pwrn, must be pro- grammed as an output to control the external switch such as the mic2025-2. switch on is requested by the usb host through the setportfeature(port_power) request. switch off is executed upon receipt of a clearportfeature(port_power) or upon detecting an overcurrent condition. the firmware clears the power control bit. only if all of the power control bits of ports 2 and 3 are cleared should the firmware de- assert the pwrn pin. 2. individual power switching ? two microcontroller gpio pins, pwr2n and pwr3n, must be assigned for each usb port to control the external switch such as the mic2026-2. each of the power control bits controls one pwrxn. 3. multiple ganged overcurrent protection ? overcurrent sensing is grouped physi- cally into one or more gangs, but reported individually.
91 3355c?usb?4/05 at43usb325 figure 8-1 shows a simplified diagram of a power management circuit of an at43usb325 based hub design with global overcurrent protection and ganged power switching. figure 8-1. port power management ctl flg in out switch at43usb325 gnd vcc pwrn ovcn port3_power port3_gnd port4_power port4_gnd bus_power gnd port5_gnd port5_power port2_gnd port2_power
92 3355c?usb?4/05 at43usb325 8.5 suspend and resume the at43usb325 enters suspend only when requested by the usb host through bus inactivity for at least 3 ms. the usb hardware would det ect this request, sets the glb_susp bit of sprsr, suspend/resume register, and interrupts the microcontroller if the interrupt is enabled. the microcontroller should shut down any peripheral activity and enter the power down mode by setting the se and sm bits of mcucr and t hen executes the sleep instruction. the usb hardware shuts off th e oscillator and pll. 8.5.1 global resume global resume is signaled by a j to k state change on port0. the usb hardware enables the oscillator/pll, prop agates the resume signaling, and se ts the rsm bit of the sprsr, which generates an interrupt. the microcontroller starts executing where it left off and services the interrupt. as part of the isr, the firmware clears the glb_susp bit. 8.5.2 remote wakeup while the at43usb325 is in global suspend, resu me signaling is also possible through remote wakeup if the remote wakeup feature is enabled. remote wakeup is defined as a port connect, port disconnect or resume signaling received at a downstream port or, in case of the embedded function, through an external interrupt. a remote wakeup initiated at a downstream port is similar in many respects to a global resume. the usb hardware enables the osc illator/pll, propagates the resu me signaling, and sets the rsm bit of the sprsr which generates an interrupt. the microcontroller starts executing where it left off and services the interrupt. as part of the isr, the firmware clears the glb_susp bit. a remote wakeup from the embedded function is initiated through int0 or the external interrupt, int1, which enables the oscillator/pll and the usb hardware. the usb hardware drives resume signaling and sets the frmwup and rs m bits of sprsr which generates an inter- rupt to the microcontroller. the microcontroller st arts executing where it left off and services the interrupt. as part of the isr, the firmware clears the glb susp bit. at completion of resume signaling, the usb hardware sets the port suspend status change bits of the hub port status change registers. 8.5.3 selective suspend and resume see section on hub port control register, hpcon.
93 3355c?usb?4/05 at43usb325 8.5.4 suspend and resume process 8.5.4.1 global suspend the host stops sending packets, the hardware detects this as global suspend signaling and stops all downstream signaling. finally, the hardware asserts the glb_susp interrupt. 8.5.4.2 global resume the host resumes signaling, the hardware detects this as global resume and propagates this signaling to all downstream ports . finally, the hardware enables t he oscillator and asserts the rsm interrupt. hardware firmware 1. host stops sending packets 2. global suspend signaling detected 3. stop downstream signaling 4. set gbl sus bit interrupt 5. shut down any peripheral activity 6. set sleep enable and sleep mode bits of mcucr 7. set gpio to low power state if required 8. set uovcer bit 2 9. execute sleep instruction 10. sleep bit detected 11. shut off oscillator hardware firmware 1. host resumes signaling 2. resume signaling detected 3. propagate signaling downstream 4. enable oscillator 5. set rsm bit interrupt 6. reset rsm and gbl susp bits 7. restore gpio states if required 8. clear uovcer bit 2 9. enable peripheral activity
94 3355c?usb?4/05 at43usb325 8.5.4.3 remote wake-up, downstream ports the hardware detects a connect/disconnect/port resume and propagates resume signaling upstream. finally, the hardware enables the oscillator and asserts the rsm interrupt. 8.5.4.4 remote wake-up, embedded function the hardware detects an int0/int1 and propagates resume signaling upstream. finally, the hardware enables the osc illator and asserts the rsm and frwup interrupts. 8.5.4.5 selective suspend, downstream ports hardware firmware 1. connect/disconnect/port resume detected 2. propagate resume signaling 3. enable oscillator 4. set rsm bit interrupt 5. reset rsm and gbl susp bits 6. restore gpio states if required 7. clear uovcer bit 2 8. enable peripheral activity hardware firmware 1. external event activates int0/int1 2. propagate resume signaling 3. enable oscillator 4. set rsm and frmwup bits interrupt 5. clear glb susp, rsm, frmwup bits 6. restore gpio states if required 7. clear uovcer bit 2 8. enable peripheral activity hardware firmware 1. set or clear port feature port_suspend decoded 2. write hpcon[2:0] and hpadd[2:0] bits 3. suspend or resume port per command
95 3355c?usb?4/05 at43usb325 8.5.4.6 selective suspend, embedded function 8.5.4.7 selective resume, embedded function hardware firmware 1. set port feature port_suspend decoded 2. disable port 1?s endpoints 3. set gpio to low power state if required hardware firmware 1. clear port feature port_suspend decoded 2. clear port 1 suspend status bit 3. restore gpio states if required 4. wait 23 ms, then set enable status bit and suspend change bit 5. enable port 1 endpoints 6. send updated port status at next in to endpoint1
96 3355c?usb?4/05 at43usb325 9. electrical specification 9.1 absolute maximum ratings stresses beyond those listed below may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to abso- lute maximum rating conditions for exten ded periods may affect device reliability. note: vcext is the voltage at cext1, cext2. 9.2 dc characteristics the values shown in this table are valid for ta = 0 c to 85 c, vcc = 4.4 to 5.25v, unless other- wise noted. table 9-1. absolute maximum ratings symbol parameter condition min max unit v cc5 5v power supply 5.5 v vi dc input voltage -0.3v vcext+0.3 4.6 max v vo dc output voltage -0.3 vcext+0.3 4.6 max v to operating temperature -40 +125 c ts storage temperature -65 +150 c table 9-2. power supply symbol parameter condition min max unit v cc 5v power supply 4.4 5.25 v i cc 5v supply current 40 ma i ccs suspended device current 600 ua table 9-3. usb signals: dpx, dmx symbol parameter condition min max unit v ih input level high (driven) 2.0 v v ihz input level high (floating) 2.7 v v il input level low 0.8 v v di differential input sensitivity dpx and dmx 0.2 v v cm differential common mode range 0.8 2.5 v v ol1 static output low rl of 1.5 k ? to 3.6v 0.3 v v oh1 static output high rl of 15 k ? to gnd 2.8 3.6 v v crs output signal crossover 1.3 2.0 v v in input capacitance 20 pf
97 3355c?usb?4/05 at43usb325 note: vcext is the voltage at cext1, cext2. note: xtal2 must not be used to drive other circuitry. 9.2.1 ac characteristics table 9-4. pa, pb, pc, pd, pe, pf symbol parameter condition min max unit v ol2 output low level, pa, pb, pe[0:3] iol = 4 ma 0.5 v rpu pc pull-up resistor current v = 0 90 280 a v il3 input low level, pc 0.3 vcext v v ih3 input high level, pc 0.7 vcext v v il4 input low level, pd[0,1] 0.3 vcext v v ih4 input high level, pd[0,1] 0.7 vcext v v ol4 output low level, pd[0,1] iol = 4 ma 0.3 vcext v v oh4 output high level, pd[0,1] ioh = 4 ma 0.7 vcext v c input/output capacitance 1 mhz 10 pf table 9-5. oscillator signals: xtal1, xtal2 symbol parameter condition min max unit v lh osc1 switching level 0.47 1.20 v v hl osc1 switching level 0.67 1.44 v cx1 input capacitance, xtal1 10 pf cx2 output capacitance, xtal2 10 pf c12 osc1/2 capacitance 5 pf t su start-up time 6 mhz, fundamental 2 ms dl drive level 50 w table 9-6. seeprom spi timing symbol parameter condition min max unit f sck sck clock frequency 50% duty cycle 333 333 ns t ro , t fo output rise time, fall time 10 10 ns -5 5 ns t css ssn setup time 0 20 ns t csh ssn hold time 0 20 ns t su data in setup time 10 ns t h data in hold time 2 ns t ho output hold time 0 ns t v output valid 10 ns
98 3355c?usb?4/05 at43usb325 figure 9-1. synchronous data timing note: 1. with external 27 ? series resistor. figure 9-2. full-speed load table 9-7. usb driver characteristic s, full speed operation symbol parameter condition min max unit tr rise time c l = 50 pf 4 20 ns tf fall time c l = 50 pf 4 20 ns trfm tr/tf matching 90 110 % zdrv driver output resistance (1) steady state drive 28 44 ? table 9-8. usb driver characteristics, low-speed operation symbol parameter condition min max unit tr rise time cl = 200 - 600 pf 75 300 ns tf fall time cl = 200 - 600 pf 75 300 ns trfm tr/tf matching 80 125 % sck mosi miso ssn t csh t cs t h0 t dis hi-z t v t h valid in hi-z t su t wh t wl t css v ih v il v ih v il v ih v il v oh v ol txd+ txd- r s r s c l c l c l = 50 pf
99 3355c?usb?4/05 at43usb325 figure 9-3. low-speed downstream port load note: 1. with 6.000 mhz, 100 ppm crystal. txd+ txd- r s r s c l c l c l = 200 pf to 600 pf 3.6v 1.5 k ohm table 9-9. usb source timings, full-speed operation symbol parameter condition min max unit tdrate full speed data rate (1) average bit rate 11.97 12.03 mb/s tframe frame interval (1) 0.9995 1.0005 ms trfi consecutive frame interval jitter (1) no clock adjustment 42 ns trfiadj consecutive fr ame interval jitter (1) with clock adjustment 126 ns tdj1 tdj2 source diff driver jitter to next transition for paired transitions -3.5 -4 3.5 4 ns tfdeop source jitter for differential transition to seo transitions -2 5 ns tdeop differential to eop transition skew -2 5 ns tjr1 tjr2 receiver data jitter tolerance to next transition for paired transitions -18.5 -9 18.5 9 ns tfeopt source seo interval of eop 160 175 ns tfeopr receiver seo in terval of eop 82 ns tfst width of seo interval during differential transition 14 ns
100 3355c?usb?4/05 at43usb325 figure 9-4. differential data jitter figure 9-5. differential-to-eop transit ion skew and eop width figure 9-6. receiver jitter tolerance crossover points paired transitions n*t period + t xjr2 consecutive transitions n*t period + t xjr1 t period differential data lines crossover point extended differential data lines t period diff. data-to- se0 skew n*t period + t deop source eop width: t feopt t leopt receiver eop width: t feopr t leopr t period differential data lines consecutive transitions n*t period + t jr1 consecutive transitions n*t period + t jr1 t jr t jr1 t jr2
101 3355c?usb?4/05 at43usb325 table 9-10. hub timings, full-speed operation symbol parameter condition min max unit thdd2 hub differential data delay without cable 44 ns thdj1 thdj2 hub diff driver jitter to next transition for paired transitions -3 -1 3 1 ns tfsop data bit width distortion after sop -5 5 ns tfeopd hub eop delay relative to thdd 0 15 ns tfhesk hub eop output width skew -15 15 ns table 9-11. hub timings, low-speed operation symbol parameter condition min max unit tlhdd hub differential data delay 300 ns tlhdj1 tlhdj2 tluhj1 tluhj2 downstr hub diff driver jitter to next transition, downst for paired transitions, downst to next transition, upstr for paired transitions, upstr -45 -15 -45 -45 45 15 45 45 ns tsop data bit width distortion after sop -60 60 ns tleopd hub eop delay relative to thdd 0 200 ns tlhesk hub eop output width skew -300 300 ns table 9-12. hub event timings symbol parameter condition min max unit tdcnn time to detect a downstream port connect event 2.5 2000 s tddis time to detect a disconnect event on downstream port awake hub suspended hub 2.5 2.5 2000 12000 s tursm time from detecting downstream resume to rebroadcast 100 s tdrst duration of driving reset to a downstream device only for a setportfeature (port_reset) request 10 20 s tdspdev time to evaluate device speed after reset 2.5 1000 s turlk time to detect a long k from upstream 2.5 5.5 s turlseo time to detect a long seo from upstream 2.5 5.5 s turpseo duration of repeating seo upstream 23 fs bits tudeop duration of sending seo upstream after eof1 2 fs bits
102 3355c?usb?4/05 at43usb325 figure 9-7. hub differential delay, different ial jitter and sop distortion figure 9-8. hub eop delay and eop skew differential data lines hub delay downstream t hdd1 crossover point downstream port crossover point hub delay upstream t hdd2 upstream port crossover point upstream end of cable v ss v ss v ss v ss 50% point of initial swing a. downstream hub delay with cable b. upstream hub delay without cable crossover point hub delay upstream t hdd1, t hdd2 crossover point downstream port upstream port or end of cable v ss v ss c. upstream hub delay with or without cable c. upstream eop delay with or without cable v ss a. upstream eop delay with cable b. downstream eop delay without cable t eop t eop+ crossover point extended crossover point extended crossover point extended crossover point extended downstream port upstream port t eop- t eop+ v ss 50% point of initial swing downstream port upstream end of cable v ss t eop- t eop+ v ss downstream port upstream port or end of cable v ss v ss
103 3355c?usb?4/05 at43usb325 10. ordering information 10.1 standard package options program memory ordering code package operation range sram AT43USB325E-AC 64aa lqfp commercial (0 c to 70 c) 10.2 green package options (pb/halide-fr ee/rohs compliant) program memory ordering code package operation range sram at43usb325e-au 64aa lqfp green, industrial (-40 c to 85 c) package type 64aa 64-lead, low-profile (1.4 mm) plastic quad flat package (lqfp)
104 3355c?usb?4/05 at43usb325 11. packaging information 11.1 64aa ? lqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 64aa , 64-lead, low-profile (1.4 mm) plastic quad flat package (lqfp) a 64aa 0.50(0.020) bsc pin 1 id 0.20(0.008) 0.09(0.003) 0?~7? 0.15(0.006) 0.05(0.002) 0.75(0.030) 0.45(0.018) 1.60(0.063) max 10.10(0.397) 9.90(0.389) sq sq 0.27(0.011) 0.17(0.007) 12.25(0.492) 11.75(0.463) pin 1 dimensions in millimeters and (inches) controlling dimensions: millimeters jedec standard ms-026 acb rev. a 1/15/2002
105 3355c?usb?4/05 at43usb325 12. errata sheet errata (all date codes): missed watchdog timer reset 12.1 problem there is a synchronization problem between the watchdog clock and the avr clock. even though the clock inputs to both the watchdog timer and the avr core are generated through the same crystal, the two clock sources are not going through the same pll. the avr is clocked at 12 mhz and the watchdog timer is clocked at 1mhz. the wdr (watchdog reset) instruction is a one-clock-cycle instruction. as such, when a watchdog timer rese t occurs due to a wdr, the watchdog timer may miss the reset. this happens frequently if the avr is clocked much faster than the watchdog timer. 12.2 fix/workaround a workaround is to invoke the wdr repetitively to ensure that the watchdog timer will be able to receive the reset signal. if the avr runs at 12 mhz, the wdr command must be invoked four- teen times back to back. the following is the sample code for resetting and arming the watchdog timer, assuming the avr is running at 12 mhz: asm ( "ldi r16,15\n wdr\n wdr\n wdr\n wdr\n wdr\n wdr\n wdr\n wdr\n wdr\n wdr\n wdr\n wdr\n wdr\n out 0x21,r16 " ); to disarm and disable the watchdog, do the following: asm ( "ldi r16,0x18\nldi r17,0x10\n\n out 0x21,r16\n out 0x21,r17 " ); please note that if the avr runs at 24 mhz, the wdr should be invoked twenty-six times.
106 3355c?usb?4/05 at43usb325 13. change log doc. rev. comments 3355c change: changes in the ?standard package options? on page 103 additions: added numbering to document headings 3355b data correction: timeout period data in table 6-8 on page 54 . additions: addions to table 3-4 on page 16 . added an ?errata sheet? on page 105 , a ?change log? on page 106 , and a ?table of contents? on page i .
i 3355c?usb?4/05 at43usb325 table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 description ............ .............. .............. ............... .............. .............. ............ 1 1.1pin configuration .......................................................................................................2 1.2pin assignment .........................................................................................................3 1.3signal description .....................................................................................................4 2 architectural overview ....... .............. ............... .............. .............. ............ 7 3 general-purpose register file ................ ................. ................ ............... 9 3.1x-, y- and z- registers ............................................................................................10 3.2arithmetic logic unit (alu) .....................................................................................10 3.3program memory .....................................................................................................10 3.4spi serial eeprom interface (at43usb325e only) .............................................11 3.5sram data memory ...............................................................................................12 3.6i/o memory ..............................................................................................................17 3.7usb hub .................................................................................................................18 4 functional description ............ ................ ................. ................ ............. 20 4.1on-chip power supply .............................................................................................20 4.2i/o pin characteristics .............................................................................................20 4.3oscillator and pll ...................................................................................................20 4.4reset and interrupt handling ..................................................................................21 4.5reset sources .........................................................................................................23 4.6power-on reset .......................................................................................................24 4.7external reset .........................................................................................................25 4.8watchdog timer reset ............................................................................................25 4.9non-usb related interrupt handling ......................................................................26 4.10external interrupts .................................................................................................29 4.11interrupt response time .......................................................................................29 4.12usb interrupt sources ..........................................................................................31 4.13usb endpoint interrupt sources ...........................................................................32 5 avr register set ..... ................ ................ ................. ................ ............. 40 5.1status register and stack pointer ..........................................................................40 5.2sleep modes ...........................................................................................................41
ii 3355c?usb?4/05 at43usb325 6 timer/counters ........ ................ ................ ................. ................ ............. 42 6.1timer/counter prescaler .........................................................................................42 6.28-bit timer/counter0 ...............................................................................................43 6.316-bit timer/counter1 .............................................................................................45 6.416-bit timer/counter1 operation .............................................................................46 6.5watchdog timer ......................................................................................................53 7 i/o ports ............... ................ .............. ............... .............. .............. .......... 55 7.1port a ..................................................................................................................... .56 7.2port b ..................................................................................................................... .57 7.3port c ..................................................................................................................... .58 7.4port d ..................................................................................................................... .59 7.5port e ..................................................................................................................... .60 7.6port f ..................................................................................................................... ..61 8 programming the usb module ........... .............. .............. .............. ........ 63 8.1usb function ..........................................................................................................63 8.2usb registers .........................................................................................................71 8.3endpoint registers ..................................................................................................72 8.4usb hub .................................................................................................................81 8.5suspend and resume .............................................................................................92 9 electrical specification ....... .............. ............... .............. .............. .......... 96 9.1absolute maximum ratings .....................................................................................96 9.2dc characteristics ..................................................................................................96 10 ordering information .......... .............. ............... .............. .............. ........ 103 10.1standard package options .................................................................................103 10.2green package options (pb/halide-free/rohs compliant) ................................103 11 packaging information .......... ................ ................. ................ ............. 104 11.164aa ? lqfp .....................................................................................................104 12 errata sheet ......... .............. .............. .............. .............. .............. ........... 105 12.1problem ...............................................................................................................105 12.2fix/workaround ...................................................................................................105 13 change log ................ ................ ................. ................ .............. ........... 106 table of contents.......... ................. ................ ................. ................ ........... i
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